TM4C129XKCZAD Datasheet, PDF (623/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
Register 23: HIB Tamper I/O Control (HIBTPIO), offset 0x410
The HIB Tamper I/O Control (HIBTPIO) register provides control of the Tamper I/O.
Note:
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module
registers are on the Hibernation module clock domain and have special timing requirements.
Software should make use of the WRC bit in the HIBCTL register to ensure that the required
timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored. See
“Register Access Timing” on page 567. The HIBIO register and bits RSTWK, PADIOWK and
WC of the HIBIC register do not require waiting for write to complete. Because these registers
are clocked by the system clock, writes to these registers/bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL
register has been set may produce unexpected results.
Note: Errant writes to the Tamper registers are protected by the Hibernate HIBLOCK register.
HIB Tamper I/O Control (HIBTPIO)
Base 0x400F.C000
Offset 0x410
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
GFLTR3 PUEN3 LEV3
EN3
Type RO
RO
RO
RO
RW
RW
RW
RW
RO
Reset
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
GFLTR1 PUEN1 LEV1
EN1
RO
RW
RW
RW
RW
RO
0
0
0
0
0
0
22
21
reserved
RO
RO
0
0
6
5
reserved
RO
RO
0
0
20
19
18
17
16
GFLTR2 PUEN2 LEV2
EN2
RO
RW
RW
RW
RW
0
0
0
0
0
4
3
2
1
0
GFLTR0 PUEN0 LEV0
EN0
RO
RW
RW
RW
RW
0
0
0
0
0
Bit/Field
31:28
27
Name
reserved
GFLTR3
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TMPR3 Glitch Filtering
Value Description
0 A trigger match level is ignored until the TMPR3 signal is stable
for two hibernate clocks.
1 A trigger match level is ignored until the TMPR3 signal is stable
for 3,071 Hibernate Clocks (93.7ms using 32.768 kHz).
26
PUEN3
RW
0
TMPR3 Internal Weak Pull-up Enable
Value Description
0 Pull-up disabled
1 Pull-up enabled
June 18, 2014
623
Texas Instruments-Production Data