TM4C129XKCZAD Datasheet, PDF (1097/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
Register 39: SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118
Interrupt Status Register
SHA Interrupt Status (SHA_IRQSTATUS)
Base 0x4403.4000
Offset 0x118
Type RO, reset 0x0000.0008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bit/Field
31:4
3
Name
reserved
CONTEXT_READY
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
1
Context Ready Status
Value Description
0 The context registers are not available for a new context.
1 The context input registers are available for a new context for
the next packet to be processed.
2
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
INPUT_READY
RO
0
Input Ready Status
Value Description
0 The Data FIFO is not ready to receive the next 64-byte data
block.
1 The Data FIFO (SHA_DATA_n_IN registers) is ready to receive
the next 64-byte data block.
0
OUTPUT_READY
RO
0
Output Ready Status
Value Description
0 No saved context available.
1 A saved context is available from the context output registers.
June 18, 2014
Texas Instruments-Production Data
1097