TM4C129XKCZAD Datasheet, PDF (1510/2188 Pages) Texas Instruments – Tiva Microcontroller

1-Wire Master Module
Timing Override (ONEWIRETIM) register. For example, the Master could sample 10 µs after
releasing the reset for 240 µs. Caution should be exercised to make sure the line has been pulled
high (by a pull-up) before the Master samples to avert a bogus answer-to-reset. Because the
slave may hold the line low for a longer duration than the sample time, the Master must wait for
the line to go high before starting a new command. This reset protocol is used to ensure that all
slaves are in a known state.
Figure 22-2 on page 1510 shows the details of the 1-wire reset.
Figure 22-2. 1-Wire Reset Protocol
OWIRE
480µs: Master drives 1-WIRE
240µs: Slave responds
Master
releases
If the Master is transmitting data to the slave, the signalling is as follows:
■ A 1 is signaled by the master driving and holding the line low for <15 µs. Generally, about 6 µs
is used for normal mode. The slave samples and measures the signal from falling edge and
checks the line 15 µs later (or more). If line has reverted to high, the slave registers a 1 value.
■ A 0 is signaled by the Master driving and holding the line low for 60 µs or more. Although the
slave reads just past 15 µs, the normal mode requires the line to be low for 60 µs. If the line is
still low after 15 µs, a value of 0 is registered.
Figure 22-3 on page 1511 depicts a 1-Wire Master transmitting a 1 to a slave. Figure 22-4 on page 1511
shows a 1-wire Master transmitting a 0 to a slave.
1510
Texas Instruments-Production Data
June 18, 2014