TM4C129XKCZAD Datasheet, PDF (1769/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
Register 67: Ethernet MAC Peripheral Configuration Register (EMACPC),
offset 0xFC4
The Ethernet MAC Peripheral Configuration Register (EMACPC) register configures the MAC
and PHY reset and interface parameters.
Ethernet MAC Peripheral Configuration Register (EMACPC)
Base 0x400E.C000
Offset 0xFC4
Type RW, reset 0x0080.040E
31
30
29
28
27
26
25
24
23
22
21
20
19
PHYEXT
PINTFS
reserved
DIGRESTART NIBDETDIS RXERIDLE ISOMIILL
LRR TDRRUN
Type RW
RW
RW
RW
RO
RO
RW
RO
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
1
0
0
0
0
15
14
13
12
11
10
9
8
7
6
FASTLDMODE POLSWAP MDISWAP RBSTMDIX FASTMDIX MDIXEN FASTRXDV FASTLUPD EXTFD FASTANEN
Type RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
1
0
0
0
0
5
4
FASTANSEL
RW
RW
0
0
3
ANEN
RW
1
18
17
16
FASTLDMODE
RW
RW
RW
0
0
0
2
1
0
ANMODE
PHYHOLD
RW
RW
RW
0
3
0
Bit/Field
31
Name
PHYEXT
Type
RW
Reset
0
Description
PHY Select
This bit is used to select whether the internal or an external PHY is used.
Value Description
0 Internal PHY
1 External PHY
30:28
PINTFS
RW
0
Ethernet Interface Select
This field selects the PHY interface used by the MAC.
This input is sampled during reset and an update to this register field
must result in the MAC undergoing a reset event.
This field has the following encoded values:
Value Description
0x0 MII (default) Used for internal PHY or external PHY connected
via MII.
0x1-0x3 reserved
0x4 RMII: Used for external PHY connected via RMII.
0x5-0x7 reserved
27:26
25
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DIGRESTART
RW
0
PHY Soft Restart
This bit allows the user to restart the PHY. Asserting this bit causes the
PHY logic and internal register to reset to initial conditions. This bit does
not affect the configuration bits provided by the EMACPC register, which
are stored in the PHY following a chip reset. To initiate the soft reset to
the PHY, this bit must be written to a 1 and written again to a 0.
June 18, 2014
Texas Instruments-Production Data
1769