TM4C129XKCZAD Datasheet, PDF (555/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
6 Processor Support and Exception Module
This module is an AHB peripheral that handles system-level Cortex-M4 FPU exceptions. For functions
with registers mapped into this aperture, if the function is not available on a device, then all writes
to the associated registers are ignored and reads return zeros.
6.1 Functional Description
The System Exception module provides control and status of the system-level interrupts. All the
interrupt events are ORed together before being sent to the interrupt controller, so the System
Exception module can only generate a single interrupt request to the controller at any given time.
Software can service multiple interrupt events in a single interrupt service routine by reading the
System Exception Masked Interrupt Status (SYSEXCMIS) register. The interrupt events that can
trigger a controller-level interrupt are defined in the System Exception Interrupt Mask (SYSEXCIM)
register by setting the corresponding interrupt mask bits. If interrupts are not used, the raw interrupt
status is always visible via the System Exception Raw Interrupt Status (SYSEXCRIS) register.
Interrupts are always cleared (for both the SYSEXCMIS and SYSEXCRIS registers) by writing a 1
to the corresponding bit in the System Exception Interrupt Clear (SYSEXCIC) register.
6.2 Register Map
Table 6-1 on page 555 lists the System Exception module registers. The offset listed is a hexadecimal
increment to the register's address, relative to the System Exception base address of 0x400F.9000.
Note: Spaces in the System Exception register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Table 6-1. System Exception Register Map
Offset Name
Type
Reset
Description
0x000 SYSEXCRIS
0x004 SYSEXCIM
0x008 SYSEXCMIS
0x00C SYSEXCIC
RO
RW
RO
W1C
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
System Exception Raw Interrupt Status
System Exception Interrupt Mask
System Exception Masked Interrupt Status
System Exception Interrupt Clear
See
page
556
558
560
562
6.3 Register Descriptions
All addresses given are relative to the System Exception base address of 0x400F.9000.
June 18, 2014
555
Texas Instruments-Production Data