TM4C129XKCZAD Datasheet, PDF (17/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
Figure 21-7. High-Speed Data Format .................................................................................. 1438
Figure 21-8. Master Single TRANSMIT ................................................................................ 1442
Figure 21-9. Master Single RECEIVE ................................................................................... 1443
Figure 21-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1444
Figure 21-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1445
Figure 21-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1446
Figure 21-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1447
Figure 21-14. Standard High Speed Mode Master Transmit ..................................................... 1448
Figure 21-15. Slave Command Sequence .............................................................................. 1449
Figure 22-1. 1-Wire Block Diagram ...................................................................................... 1508
Figure 22-2. 1-Wire Reset Protocol ...................................................................................... 1510
Figure 22-3. 1-Wire Master Transmitting a 1 ......................................................................... 1511
Figure 22-4. 1-Wire Master Transmitting a 0' ........................................................................ 1511
Figure 22-5. 1-Wire Master Receiving a 1 Signal from a Slave ............................................... 1512
Figure 22-6. 1-Wire Master Receiving a 0 Signal from a Slave ............................................... 1512
Figure 23-1. CAN Controller Block Diagram .......................................................................... 1538
Figure 23-2. CAN Data/Remote Frame ................................................................................. 1539
Figure 23-3. Message Objects in a FIFO Buffer .................................................................... 1548
Figure 23-4. CAN Bit Time ................................................................................................... 1552
Figure 24-1. Ethernet MAC with Integrated PHY Interface ..................................................... 1589
Figure 24-2. Ethernet MAC and PHY Clock Structure ............................................................ 1592
Figure 24-3. MII Clock Structure .......................................................................................... 1593
Figure 24-4. RMII Clock Structure ........................................................................................ 1594
Figure 24-5. Enhanced Transmit Descriptor Structure ........................................................... 1599
Figure 24-6. Enhanced Receive Descriptor Structure ............................................................ 1604
Figure 24-7. TX DMA Default Operation Using Descriptors .................................................... 1611
Figure 24-8. TX DMA OSF Mode Operation Using Descriptors .............................................. 1613
Figure 24-9. RX DMA Operation Flow .................................................................................. 1616
Figure 24-10. Networked Time Synchronization ...................................................................... 1626
Figure 24-11. System Time Update Using Fine Correction Method .......................................... 1628
Figure 24-12. Propagation Delay Calculation in Clocks Supporting Peer-to-Peer Path
Correction ....................................................................................................... 1631
Figure 24-13. Wake-Up Frame Filter Register Bank ................................................................ 1639
Figure 24-14. Integrated PHY Diagram .................................................................................. 1643
Figure 24-15. Interface to Ethernet Jack ................................................................................. 1650
Figure 25-1. USB Module Block Diagram ............................................................................. 1832
Figure 26-1. LCD Block Diagram ......................................................................................... 1841
Figure 26-2. Input and Output Clocks ................................................................................... 1844
Figure 26-3. LCD Raster Data Path ...................................................................................... 1850
Figure 26-4. Palette RAM Structure for 1, 2, and 4 Bits Per Pixel ........................................... 1852
Figure 26-5. 24 bpp Packed Data Format ............................................................................. 1854
Figure 26-6. 24 bpp Unpacked Data Format ......................................................................... 1854
Figure 26-7. 24 bpp Color RGB Remapping on LCDDATA[23:0] ............................................. 1855
Figure 26-8. 16 bpp Data Format ......................................................................................... 1855
Figure 26-9. 16 bpp Color Component Ordering .................................................................... 1855
Figure 26-10. 12 bpp Data Format ......................................................................................... 1856
Figure 26-11. 12 bpp Color Component Ordering .................................................................... 1856
Figure 26-12. 1/2/4/8 bpp Dither Output ................................................................................. 1857
June 18, 2014
17
Texas Instruments-Production Data