TM4C129XKCZAD Datasheet, PDF (1451/2188 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129XKCZAD Microcontroller
21.5
TPR = (System Clock/(2*(SCL_LP + SCL_HP)*SCL_CLK))-1;
TPR = (80 MHz/(2*(2+1)*3330000))-1;
TPR = 3
Write the I2CMTPR register with the value of 0x0000.0003.
8. To send the master code byte, software should place the value of the master code byte into the
I2CMSA register and write the I2CMCS register with the following value depending on the
required operation:
■ For Standard High-Speed mode, the I2CMCS register should be written with 0x13.
■ For Burst High-Speed mode, the I2CMCS register should be written with 0x50.
9. This places the I2C master peripheral in High-speed mode, and all subsequent transfers (until
STOP) are carried out at High-speed data rate using the normal I2CMCS command bits, without
setting the HS bit in the I2CMCS register.
10. The transaction is ended by setting the STOP bit in the I2CMCS register.
11. Wait until the transmission completes by polling the I2CMCS register's BUSBSY bit until it has
been cleared.
12. Check the ERROR bit in the I2CMCS register to confirm the transmit was acknowledged.
Register Map
Table 21-4 on page 1452 lists the I²C registers. All addresses given are relative to the I²C base address:
■ I²C 0: 0x4002.0000
■ I²C 1: 0x4002.1000
■ I²C 2: 0x4002.2000
■ I²C 3: 0x4002.3000
■ I²C 4: 0x400C.0000
■ I²C 5: 0x400C.1000
■ I²C 6: 0x400C.2000
■ I²C 7: 0x400C.3000
■ I²C 8: 0x400B.8000
■ I²C 9: 0x400B.9000
Note that the I²C module clock must be enabled before the registers can be programmed (see
page 408). There must be a delay of 3 system clocks after the I²C module clock is enabled before
any I²C module registers are accessed.
The hw_i2c.h file in the TivaWare^™ Driver Library uses a base address of 0x800 for the I²C slave
registers. Be aware when using registers with offsets between 0x800 and 0x818 that TivaWare™
for C Series uses an offset between 0x000 and 0x018 with the slave base address.
June 18, 2014
Texas Instruments-Production Data
1451