OMAP3515DCBC Datasheet, PDF (6/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the OMAP3515/03 Applications Processor.
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OMAP Applications Processor
MPU
Subsystem
ARM Cortex-
A8^TM Core
16K/16K L1$
L2$
256K
POWERVR
SGX^TM
Graphics
Accelerator
(3515 Only)
32
Channel
System
DMA
LCD Panel
CVBS
or
S-Video
Parallel
Amp
TV
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV→QCIF Support
Camera
(Parallel)
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
and
Preview
HS USB
Host
(with
USB
TTL)
HS
USB
OTG
32
64K
On-Chip
RAM
2KB
Public/
62KB
Secure
64
64
32
32 32 32
32
Async
64
32
64
64
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
32
112K
On-Chip
ROM
80KB
Secure/
32KB
BOOT
64
SMS:
SDRAM
Memory
Scheduler/
Rotation
SDRC:
SDRAM
Memory
Controller
32
GPMC:
General
Purpose
Memory
Controller
NAND/
NOR
Flash,
SRAM
32
32
L4 Interconnect
Peripherals:
3xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 6xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
2xMailboxes
12xGPTimers, 2xWDT,
32K Sync Timer
System
Controls
PRCM
2xSmartReflex^TM
Control
Module
External
Peripherals
Interfaces
External and
Stacked Memories
Emulation
Debug: SDTI, ETM, JTAG,
Coresight^TM DAP
Figure 1-1. OMAP3515/03 Functional Block Diagram
6
OMAP3515/03 Applications Processor
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