OMAP3515DCBC Datasheet, PDF (189/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

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OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
C_LOAD
Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode (continued)
TIMING CONDITION PARAMETER
Output load capacitance
VALUE
8.6
UNIT
pF
Table 6-29. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode⁽¹⁾
NO.
PARAMETER
1.15 V
ISP17
ISP18
ISP18
ISP19
t_c(pclk)
t_W(pclkH)
t_W(pclkL)
t_dc(pclk)
t_j(pclk)
t_su(dV-pclkH)
Cycle time⁽²⁾, cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
Cycle jitter⁽⁴⁾, cam_pclk
Setup time, cam_d[11:0] valid before cam_pclk
rising edge
MIN
MAX
13.3
0.5*P ⁽³⁾
0.5*P ⁽³⁾
667
133
1.82
ISP20 t_h(pclkH-dV)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
1.82
ISP21 t_su(dV-vsH)
Setup time, cam_vs valid before cam_pclk rising
edge
1.82
ISP22
ISP23
t_h(pclkH-vsV)
t_su(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
Setup time, cam_hs valid before cam_pclk rising
edge
1.82
1.82
ISP24
ISP25
t_h(pclkH-hsV)
t_su(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
Setup time, cam_wen valid before cam_pclk rising
edge
1.82
1.82
ISP26 t_h(pclkH-hsV)
Hold time, cam_wen valid after cam_pclk rising
edge
1.82
ISP27 t_su(dV-fldH)
Setup time, cam_fld valid before cam_pclk rising
edge
1.82
ISP28 t_{h(pclkH-fldV)}
Hold time, cam_fld valid after cam_pclk rising edge
1.82
(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(2) Related with the input maximum frequency supported by the ISP module.
(3) P = cam_lclk period in ns.
(4) Maximum cycle jitter supported by cam_pclk input clock.
1.0 V
MIN
MAX
22.2
0.5*P ⁽³⁾
0.5*P ⁽³⁾
1111
200
3.25
3.25
3.25
3.25
3.25
3.25
3.25
3.25
3.25
3.25
UNIT
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-30. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
ISP15
ISP16
ISP16
t_c(xclk)
t_W(xclkH)
t_W(xclkL)
t_dc(xclk)
t_j(xclk)
t_R(xclk)
t_F(xclk)
Cycle time⁽¹⁾, cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
Jitter standard deviation⁽³⁾, cam_xclk
Rise time, cam_xclk
Fall time, cam_xclk
MIN
MAX
4.6
0.5*PO ⁽²⁾
0.5*PO ⁽²⁾
231
33
0.93
0.93
MIN
MAX
4.6
ns
0.5*PO ⁽²⁾
ns
0.5*PO ⁽²⁾
ns
231
ps
33
ps
0.93
ns
0.93
ns
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see
the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98
(2) PO = cam_xclk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 189