OMAP3515DCBC Datasheet, PDF (45/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

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OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
AH6, U1, R4, NA
J1, J2, G28,
F1, F2, D16,
C16, C28,
B5, B8, B12,
B18, B22,
A5, A8, A12,
A18, A22
AG20, AG21, NA
AG27, AF8,
AF16, AF23,
AE8, AE16,
AE23, AE27,
AD3, AD4,
W4, H28,
F25, F26
W16
NA
K15
NA
AA16
NA
AA14
NA
K25, P25 NA
V25
NA
Y26
NA
AA26, AG2, NA
AG3, AG6,
AF12, AF20,
AE12, AE20,
AC25, AC26,
AG16, AH21,
Y12, Y13,
Y17, Y25,
W3, W10,
W13, W14,
W17, W19,
W25, V9,
V10, V19,
U2, U9, T20,
R19, R20,
R26, P3, P4,
P9, P10,
P19, N9,
M20, M28,
L19, L20,
L26, K9,
K10, K12,
K16, K17,
K19, J3, J12,
J13, J16,
J17, G27,
E3,E4, D7,
D10, D13,
D19, D21,
C7, C10,
C13, C19,
C22, B2,
B27, A3, A26
AH20, AA15, NA
V4, L21
vdds_mem 0
vdds
0
vdds_sram 0
vdds_dpll_dll 0
vdds_dpll_pe 0
r
vdds_wkup_ 0
bg
vdds_mmc1, 0
vdds_mmc1a
vdda_dac 0
vssa_dac 0
vss
0
cap_vdd_d, 0
cap_vdd_wk
up,
cap_vdd_sra
m_mpu,
cap_vdd_sra
m_core
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
PWR
BALL
RESET
STATE [6]
-
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
-
-
IO CELL [13]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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-
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TERMINAL DESCRIPTION
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