OMAP3515DCBC Datasheet, PDF (36/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
hsusb3_tll_n 5
IO
xt
mm3_rxdm 6
IO
safe_mode 7
AF6
NA
mcbsp3_dx 0
IO
uart2_cts 1
I
gpio_140 4
IO
hsusb3_tll_ 5
IO
data4
safe_mode 7
AE6
NA
mcbsp3_dr 0
I
uart2_rts 1
O
gpio_141 4
IO
hsusb3_tll_ 5
IO
data5
safe_mode 7
AF5
NA
mcbsp3_ 0
IO
clkx
uart2_tx
1
O
gpio_142 4
IO
hsusb3_tll_ 5
IO
data6
safe_mode 7
AE5
NA
mcbsp3_fsx 0
IO
uart2_rx
1
I
gpio_143 4
IO
hsusb3_tll_ 5
IO
data7
safe_mode 7
AB26
NA
uart2_cts 0
I
mcbsp3_dx 1
IO
gpt9_pwm_e 2
IO
vt
gpio_144 4
IO
safe_mode 7
AB25
NA
uart2_rts 0
O
mcbsp3_dr 1
I
gpt10_pwm_ 2
IO
evt
gpio_145 4
IO
safe_mode 7
AA25
NA
uart2_tx
0
O
mcbsp3_ 1
IO
clkx
gpt11_pwm 2
IO
_evt
gpio_146 4
IO
safe_mode 7
AD25
NA
uart2_rx
0
I
mcbsp3_fsx 1
IO
gpt8_pwm_e 2
IO
vt
gpio_147 4
IO
safe_mode 7
AA8
NA
uart1_tx
0
O
gpio_148 4
IO
safe_mode 7
AA9
NA
uart1_rts 0
O
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
IO CELL [13]
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
36
TERMINAL DESCRIPTION
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