OMAP3515DCBC Datasheet, PDF (41/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

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OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
gpio_181 4
IO
safe_mode 7
V3
NA
mcspi2_cs1 0
O
gpt8_pwm_e 1
IO
vt
hsusb2_tll_ 2
IO
data3
hsusb2_
3
IO
data3
gpio_182 4
IO
mm2_txen_n 5
IO
safe_mode 7
AE25
NA
sys_32k
0
I
AE17
NA
sys_xtalin 0
I
AF17
NA
sys_xtalout 0
O
AF25
NA
sys_clkreq 0
IO
gpio_1
4
IO
safe_mode 7
AF26
NA
sys_nirq
0
I
gpio_0
4
IO
safe_mode 7
AH25
NA
sys_
0
I
nrespwron
AF24
NA
sys_
0
IOD
nreswarm
gpio_30
4
IO
safe_mode 7
AH26
NA
sys_boot0 0
I
gpio_2
4
IO
safe_mode 7
AG26
NA
sys_boot1 0
I
gpio_3
4
IO
safe_mode 7
AE14
NA
sys_boot2 0
I
gpio_4
4
IO
safe_mode 7
AF18
NA
sys_boot3 0
I
gpio_5
4
IO
safe_mode 7
AF19
NA
sys_boot4 0
I
mmc2_dir_da 1
O
t2
gpio_6
4
IO
safe_mode 7
AE21
NA
sys_boot5 0
I
mmc2_dir_da 1
O
t3
gpio_7
4
IO
safe_mode 7
AF21
NA
sys_boot6 0
I
gpio_8
4
IO
safe_mode 7
AF22
NA
sys_off_
0
O
mode
gpio_9
4
IO
safe_mode 7
AG25
NA
sys_clkout1 0
O
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
L
L
7
vdds
Yes
Z
I
NA
vdds
Yes
Z
I
NA
vdds
NA
Z
O
NA
vdds
NA
0
1
0
vdds
Yes
H
H
7
vdds
Yes
Z
I
NA
vdds
Yes
0
1 (PU)
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
Z
Z
0
vdds
Yes
0
L
7
vdds
Yes
L
L
7
vdds
Yes
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
IO CELL [13]
4
PU/ PD
LVCMOS
NA
NA
LVCMOS
NA
NA
LVCMOS
NA
NA
LVCMOS
8
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
NA
NA
LVCMOS
8
PU/ PD
LVCMOS
Open Drain
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
8
PU/ PD
LVCMOS
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