OMAP3515DCBC Datasheet, PDF (188/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
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cam_xclki
ISP1
ISP2
ISP2
cam_pclk
ISP3
ISP4
ISP4
cam_vs
ISP5
ISP6
cam_hs
ISP7
ISP8
cam_d[7:0]
ISP9
D(0)
D(n-3) D(n-2) D(n-1)
ISP10
D(0)
D(1)
D(n-1)
cam_wen
cam_fld
ISP11
ISP12
030-059
Figure 6-24. ISP – 8-bit Packed SYNC – Progressive Mode^{(1)(2)(3)(4)(5)}
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.
(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the
data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external
memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of
cam_fld is programmable.
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer
a YCbCr data stream or compressed stream to memory at very high speed.
(5) In cam_xclki; I is equal to a or b.
6.5.1.1.1.3 12-Bit SYNC Normal – Interlaced Mode
Table 6-29 and Table 6-30 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-25).
Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
VALUE
2.7
2.7
UNIT
ns
ns
188 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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