OMAP3515DCBC Datasheet, PDF (119/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

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vdd_mpu
vdds_dpll_dll
vdds_wkup_bg
cap_vdd_wkup
vdds_mem
BandGap
LDO3
1.0 V/1.2 V
WKUP
EMU
BCK
MEM
DLL/DCDL
OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
LDO
in 1.8 V
out 1.2 V
MPU
DPLL_MPU
SRAM 1 LDO
0 V/1.0 V/1.2 V
SRAM1
ARRAY
cap_vdd_sram_mpu
vdds
vdds_sram
vdd_mpu domain
vpp
vdd_core
vdds_mmc1
vdds_mmc1a
eFUSE
MMC1
vdds_dpll_per
vdda_dac
Dual Video DAC
LDO
in 1.8 V
out 1.2 V
DPLL_CORE
Core
LDO
HSDIVIDER
vdd_core domain
SRAM 2 LDO
0 V/1.0 V/1.2 V
SRAM2
ARRAY
LDO
in 1.8 V
out 1.2 V
DPLL4
Periph1
LDO
HSDIVIDER
LDO
in 1.8 V
out 1.2 V
DPLL5
Periph2
OMAP Device
cap_vdd_sram_core
tv_ref
(for capacitor)
vss
vssa_dac
030-003
Figure 3-1. OMAP3515/03 Power Domains
This power domain segmentation switches off (or places in retention state) domains that are unused while
keeping others active. This implementation is based on internal switches that independently control each
power domain.
A power domain regular logic is attached to one of the device V_DD supplies through a primary domain
switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of
the domain. Embedded switches are implemented for all power domains except the wake-up domain. This
allows the domain to be powered off, if not being used, to give maximum power savings. For more
information, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature
number SPRUFA5].
All domain output signals at the interface between power domains are connected through isolation latch
cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface
state at the domain boundaries.
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ELECTRICAL CHARACTERISTICS 119