OMAP3515DCBC Datasheet, PDF (171/264 Pages) Texas Instruments – OMAP3515/03 Applications Processor

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gpmc_fclk
OMAP3515/03 Applications Processor
SPRS505F – FEBRUARY 2008 – REVISED SEPTEMBER 2009
gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_a[16:1]_d[15:0]
FA9
FA10
FA10
FA3
FA12
FA25
FA29
Valid Address (LSB)
FA1
Address (MSB)
FA0
FA0
FA27
FA28
Data OUT
gpmc_waitx
gpmc_io_dir
OUT
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing
030-031
6.4.1.3 GPMC/NAND Flash Interface Timing
Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see
Figure 6-13 through Figure 6-16) and electrical characteristic conditions.
Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
t_R
t_F
Output Conditions
Input signal rise time
Input signal fall time
C_LOAD
Output load capacitance
VALUE
1.8
1.8
15.94
UNIT
ns
ns
pF
Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters⁽¹⁾⁽²⁾
NO.
PARAMETER
GNFI1
GNFI2
Maximum output data generation delay from
internal functional clock
Maximum input data capture delay by internal
functional clock
1.15 V
MIN
MAX
6.5
4
1.0 V
MIN
MAX
9.1
5.6
0.9 V
MIN
MAX
13.7
8.1
UNIT
ns
ns
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
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TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 171