MSP430FR5969_14 Datasheet, PDF (59/132 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704B – OCTOBER 2012 – REVISED MAY 2014
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN, OUT
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input and output
Power supply
Ground supply
6.8 FRAM Memory
The FRAM memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-
system by the CPU. Features of the FRAM memory include:
• Ultra-low-power ultra-fast-write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
Wait States
NOTE
For MCLK frequencies > 8 MHz, wait states must be configured following the flow described
in the "Wait State Control" section of the "FRAM Controller (FRCTRL)" chapter in the
MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide
(SLAU367).
6.9 Memory Protection Unit Including IP Encapsulation
The FRAM memory can be protected from inadvertent CPU execution, read access, or write access by
the MPU. Features of the MPU include:
• IP encapsulation with programmable boundaries in steps of 1KB (prevents reads from "outside"; for
example, JTAG or non-IP software).
• Main memory partitioning is programmable up to three segments in steps of 1KB.
• Each segment's access rights can be individually selected (main and information memory).
• Access violation flags with interrupt capability for easy servicing of access violations.
6.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. Peripherals can be
handled using all instructions. For complete module descriptions, see the MSP430FR58xx,
MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367).
6.10.1 Digital I/O
There are up to four 8-bit I/O ports implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all ports.
• Read and write access to port control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch functionality is supported on all pins of ports P1, P2, P3, P4, and PJ.
• No cross-currents during start-up.
Copyright © 2012–2014, Texas Instruments Incorporated
Detailed Description
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471