MSP430FR5969_14 Datasheet, PDF (51/132 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704B – OCTOBER 2012 – REVISED MAY 2014
5.15 Emulation and Debug
Table 5-35. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP MAX UNIT
I_JTAG
f_SBW
t_SBW,Low
t_{SBW, En}
Supply current adder when JTAG active (but not clocked)
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
2.2 V, 3.0 V
40 100 μA
0
10 MHz
0.04
15 μs
110 μs
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency - 4-wire JTAG⁽²⁾
15
2.2 V
0
3.0 V
0
100 μs
16 MHz
16 MHz
R_internal
Internal pulldown resistance on TEST
f_TCLK
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by f_SYSTEM)
t_{TCLK,Low/High}
TCLK low or high clock pulse duration, no FRAM access
f_TCLK,FRAM
TCLK/MCLK frequency during JTAG access, including FRAM
access (limited by f_SYSTEM with no FRAM wait states)
t_{TCLK,FRAM,Low/Hig TCLK low or high clock pulse duration, including FRAM accesses}
h
2.2 V, 3.0 V
20
35
50 kΩ
16 MHz
25 ns
4 MHz
100 ns
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
Copyright © 2012–2014, Texas Instruments Incorporated
Specifications
51
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MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471