MSP430FR5969_14 Datasheet, PDF (113/132 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704B – OCTOBER 2012 – REVISED MAY 2014
7.1.6 General Layout Recommendations
• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the
application report MSP430 32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
• Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
• Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
(SLAA530) for guidelines.
7.1.7 Do's and Don'ts
It is recommended to power AVCC and DVCC pins from the same source. At a minimum, during power
up, power down, and device operation, the voltage difference between AVCC and DVCC must not exceed
the limits specified in the Absolute Maximum Ratings section. Exceeding the specified limits may cause
malfunction of the device including erroneous writes to RAM and FRAM.
7.2 Peripheral- and Interface-Specific Design Information
7.2.1 ADC12_B Peripheral
7.2.1.1 Partial Schematic
Using an
External
Positive
Reference
Using an
External
Negative
Reference
+
10 µF 4.7 µF
+
10 µF 4.7 µF
AVSS
VREF+/VEREF+
VEREF-
Figure 7-5. ADC12_B Grounding and Noise Considerations
7.2.1.2 Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. A noise-free design using
separate analog and digital ground planes with a single-point connection is recommend to achieve high
accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as specified in the Reference module's I_O(VREF+)
specification.
Copyright © 2012–2014, Texas Instruments Incorporated
Applications, Implementation, and Layout 113
Submit Documentation Feedback
Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471