MSP430FR5969_14 Datasheet, PDF (45/132 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP430FR5969, MSP430FR59691, MSP430FR5968, MSP430FR5967
MSP430FR5959, MSP430FR5958, MSP430FR5957
MSP430FR5949, MSP430FR5948, MSP430FR5947, MSP430FR59471
SLAS704B – OCTOBER 2012 – REVISED MAY 2014
Table 5-24. 12-Bit ADC, Linearity Parameters with External Reference⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Resolution
Number of no missing code
output-code bits
12
bits
E_I
Integral linearity error (INL)
for differential input
1.2 V ≤ V_R+ - V_R-≤ AV_CC
±1.8 LSB
E_I
Integral linearity error (INL)
for single ended inputs
1.2 V ≤ V_R+ - V_R-≤ AV_CC
±2.2 LSB
E_D
Differential linearity error
(DNL)
-0.99
+1.0 LSB
E_O
Offset error^{(2) (3)}
ADC12VRSEL = 0x2 or 0x4 without TLV calibration,
TLV calibration data can be used to improve the
parameter ⁽⁴⁾
±0.5 ±1.5 mV
E_G,ext
Gain error
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the
parameter ⁽⁴⁾,
VR+ = 2.5 V, VR- = AVSS
±0.8 ±2.5 LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR- = AVSS
±1
±20 LSB
E_T,ext
Total unadjusted error
With external voltage reference without internal buffer
(ADC12VRSEL = 0x2 or 0x4) without TLV calibration,
TLV calibration data can be used to improve the
parameter ⁽⁴⁾,
VR+ = 2.5 V, VR- = AVSS
±1.4 ±3.5 LSB
With external voltage reference with internal buffer
(ADC12VRSEL = 0x3),
VR+ = 2.5 V, VR- = AVSS
±1.4 ±21.0 LSB
(1) See Table 5-26 and Table 5-32 electrical sections for more information on internal reference performance and refer to the application
report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your
application with the choice of internal versus external reference.
(2) Offset is measured as the input voltage (at which ADC output transitions from 0 to 1) minus 0.5 LSB.
(3) Offset increases as IR drop increases when VR- is AVSS.
(4) For details, see the Device Descriptor Table section in the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, and MSP430FR69xx
Family User's Guide (SLAU367).
Table 5-25. 12-Bit ADC, Dynamic Performance for Differential Inputs with External Reference⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SNR Signal-to-noise
ENOB Effective number of bits⁽²⁾
VR+ = 2.5 V, VR- = AVSS
VR+ = 2.5 V, VR- = AVSS
68
71
dB
10.7 11.2
bits
(1) See Table 5-26 and Table 5-32 electrical sections for more information on internal reference performance and refer to the application
report Designing With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your
application with the choice of internal versus external reference.
(2) ENOB = (SINAD-1.76)/6.02
Table 5-26. 12-Bit ADC, Dynamic Performance for Differential Inputs with Internal Reference⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ENOB
PARAMETER
Effective number of bits⁽²⁾
TEST CONDITIONS
VR+ = 2.5 V, VR- = AVSS
MIN TYP MAX UNIT
10.3 10.7
Bits
(1) See Table 5-32 electrical section for more information on internal reference performance and refer to the application report Designing
With the MSP430FR59xx and MSP430FR58xx ADC (SLAA624) for details on optimizing ADC performance for your application with the
choice of internal versus external reference.
(2) ENOB = (SINAD-1.76)/6.02
Copyright © 2012–2014, Texas Instruments Incorporated
Specifications
45
Submit Documentation Feedback
Product Folder Links: MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959
MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471