BQ25600 Datasheet, PDF (55/66 Pages) Texas Instruments – I2C Controlled 3.0-A, Single Cell Battery Charger With up-to 40-V Overvoltage Protection Controller for High-Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

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10 Layout
bq25600, bq25600D
SLUSCJ4 – JUNE 2017
10.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 51) is important to prevent electrical
andmagnetic field radiation and high frequency resonant problems.
IMPORTANT
It is essential to follow this specific layout PCB order.
1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper
trace connection or GND plane.
2. Put output capacitor near to the inductor and the IC.
3. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
4. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other
trace or plane.
5. It is OK to connect all grounds together to reduce PCB size and improve thermal dissipation.
6. Try to avoid ground planes in parallel with high frequency traces in other layers.
See the EVM design for the recommended component placement with trace and via locations.
10.2 Layout Example
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Figure 51. High Frequency Current Path
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