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BQ25600 Datasheet, PDF (5/66 Pages) Texas Instruments – I2C Controlled 3.0-A, Single Cell Battery Charger With up-to 40-V Overvoltage Protection Controller for High-Input Voltage and Narrow Voltage DC (NVDC) Power Path Management
www.ti.com
NAME
ACDRV
BAT
BATSNS
BTST
CE
D+
D–
GND
INT
PG
PMID
PSEL
QON
REGN
SCL
SDA
STAT
SW
SYS
Pin
bq25600
WCSP
B5
C1
D1
E1
F1
F3
bq25600D
WCSP
B5
C1
D1
E1
F1
F3
C3
C3
E3
E3
—
C5
—
D5
A1
A1
B1
B1
F4
F4
D5
—
A3
A3
B3
B3
C5
—
D4
D4
C4
C4
F5
F5
E4
E4
E5
E5
A2
A2
B2
B2
C2
C2
D2
D2
E2
E2
F2
F2
Pin Functions
bq25600, bq25600D
SLUSCJ4 – JUNE 2017
TYPE (1)
DESCRIPTION
Charge pump output to drive external N-channel MOSFET (OVPFET). ACDRV voltage
AO
is 6 V above VBUS when VAC voltage is below ACOV threshold (REG06[6:5]) and
above UVLO.
Battery connection point to the positive terminal of the battery pack. The internal
P
current sensing resistor is connected between SYS and BAT. Connect a 10 µF closely
to the BAT pin.
Battery voltage sensing pin for charge current regulation. in order to minimize the
AIO
parasitic trace resistance during charging, BATSNS pin is connected to the actual
battery pack as close as possible.
P
PWM high side driver positive supply. internally, the BTST is connected to the cathode
of the boost-strap diode. Connect the 0.047-μF bootstrap capacitor from SW to BTST.
DI
Charge enable pin. When this pin is driven low, battery charging is enabled.
Positive line of the USB data line pair. D+/D– based USB host/charging port detection.
AIO
The detection includes data contact detection (DCD), primary and secondary detection
in BC1.2.
Negative line of the USB data line pair. D+/D– based USB host/charging port
AIO
detection. The detection includes data contact detection (DCD), primary and secondary
detection in BC1.2.
—
Open-drain interrupt Output. Connect the INT to a logic rail through 10-kΩ resistor. The
DO
INT pin sends active low, 256-µs pulse to host to report charger device status and
fault.
Open drain active low power good indicator. Connect to the pull up rail through 10 kΩ
DO
resistor. LOW indicates a good input source if the input voltage is between UVLO and
ACOV, above SLEEP mode threshold, and current limit is above 30 mA.
Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of
DO
HSFET. Given the total input capacitance, put 1 μF on VBUS to GND, and the rest
capacitance on PMID to GND.
Power source selection input. High indicates 500 mA input current limit. Low indicates
DI
2.4A input current limit. Once the device gets into host mode, the host can program
different input current limit to IINDPM register.
BATFET enable/reset control input. When BATFET is in ship mode, a logic low of
tSHIPMODE duration turns on BATFET to exit shipping mode. When VBUS is not
DI
plugged–in, a logic low of tQON_RST (minimum 8 s) duration resets SYS (system power)
by turning BATFET off for tBATFET_RST (minimum 250 ms) and then re-enable BATFET
to provide full system power reset. The pin contains an internal pull-up to maintain
default high logic.
PWM low side driver positive supply output. internally, REGN is connected to the
P
anode of the boost-strap diode. Connect a 4.7-μF (10-V rating) ceramic capacitor from
REGN to analog GND. The capacitor should be placed close to the IC.
DI
I2C interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
DIO
I2C interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
Open-drain interrupt output. Connect the STAT pin to a logic rail via 10-kΩ resistor.
The STAT pin indicates charger status.
DO
Charge in progress: LOW
Charge complete or charger in SLEEP mode: HIGH
Charge suspend (fault response): Blink at 1Hz
Switching node connecting to output inductor. Internally SW is connected to the source
P
of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047-μF
bootstrap capacitor from SW to BTST.
P
Converter output connection point. The internal current sensing resistor is connected
between SYS and BAT. Connect a 20 µF closely to the SYS pin.
(1) AI = Analog input, AO = Analog Output, AIO = Analog input Output, DI = Digital input, DO = Digital Output, DIO = Digital input Output, P
= Power
Copyright © 2017, Texas Instruments Incorporated
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