BQ25600 Datasheet, PDF (18/66 Pages) Texas Instruments – I2C Controlled 3.0-A, Single Cell Battery Charger With up-to 40-V Overvoltage Protection Controller for High-Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

bq25600, bq25600D
SLUSCJ4 – JUNE 2017
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7.3 Feature Description
7.3.1 Power-On-Reset (POR)
The device powers internal bias circuits from the higher voltage of VBUS and BAT. When VBUS rises above
V_{VBUS_UVLOZ} or BAT rises above V_{BAT_UVLOZ} , the sleep comparator, battery depletion comparator and BATFET
driver are active. I²C interface is ready for communication and all the registers are reset to default value. The
host can access all the registers after POR.
7.3.2 Device Power Up from Battery without Input Source
If only battery is present and the voltage is above depletion threshold (V_{BAT_DPL_RISE)}, the BATFET turns on and
connects battery to system. The REGN stays off to minimize the quiescent current. The low RDSON of BATFET
and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time.
The device always monitors the discharge current through BATFET (Supplement Mode). When the system is
overloaded or shorted (I_BAT > I_{BATFET_OCP}), the device turns off BATFET immediately and set BATFET_DIS bit to
indicate BATFET is disabled until the input source plugs in again or one of the methods described in BATFET
Enable (Exit Shipping Mode) is applied to re-enable BATFET.
7.3.3 Power Up from Input Source
When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the
bias circuits. It detects and sets the input current limit before the buck converter is started. The power up
sequence from input source is as listed:
1. Power Up OVPFET
2. Power Up REGN LDO
3. Poor Source Qualification
4. IInput Source Type Detection is based on D+/D– or PSEL to set default input current limit (IINDPM) register
or input source type.
5. Input Voltage Limit Threshold Setting (VINDPM threshold)
6. Converter Power-up
7.3.3.1 Power Up OVPFET
The external OVPFET provides an additional layer of voltage protection for the device. The external OVPFET is
enabled when all the below conditions are valid.
• VAC above V_{VAC_PRESENT}
• VAC below V_BAT + V_SLEEP in boost mode
• VAC below V_{VAC_OV}
• After t_DEB (15ms nom.) delay is completed
• OVPFET_DIS bit is cleared and EN_HIZ bit is cleared
If one of the above conditions is not valid, the device is in high impedance state (HIZ) with REGN LDO off. The
device draws less current (I_{VBUS_HIZ}) from VBUS during a HIZ state. The battery powers the system when the
device is in a HIZ state.
As shown in Figure 10, V_{VAC_PRESENT(rising)} < V_VAC < V_{VAC_OV(rising)} must be valid before ACDRV goes high.
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