BQ25600 Datasheet, PDF (32/66 Pages) Texas Instruments – I2C Controlled 3.0-A, Single Cell Battery Charger With up-to 40-V Overvoltage Protection Controller for High-Input Voltage and Narrow Voltage DC (NVDC) Power Path Management

bq25600, bq25600D
SLUSCJ4 – JUNE 2017
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SDA
SCL
Data line stable;
Data valid
Change of data
allowed
Figure 21. Bit Transfer on the I²C Bus
7.3.11.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the mAster. The
bus is considered busy after the START condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
START (S)
STOP (P)
Figure 22. TS START and STOP conditions
7.3.11.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the mAster into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
SDA
MSB
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
SCL
S or Sr
START or
Repeated
START
1
2
7
8
9
ACK
1
2
Figure 23. Data Transfer on the I²C Bus
8
9
ACK
P or Sr
STOP or
Repeated
START
7.3.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge ninth clock pulse, are generated by the mAster. The transmitter releases the SDA line during the
acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
When SDA remains HIGH during the ninth clock pulse, this is the Not Acknowledge signal. The mAster can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
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