DS90UB926Q Datasheet, PDF (49/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
data source. The second FRC block, FRC2, follows the white balance block and is intended to be used when fine adjustment of
color temperature is required on an 18-bit color display, or when a 24-bit source drives an 18-bit display with a white balance LUT
calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user must provide a description of the display timing control signals. The
timing mode, “sync mode” (HS, VS) or “DE only” must be specified, along with the active polarity of the timing control signals. All
this information is entered to DS90UB926Q control registers via the serial bus interface.
Adaptive Hi-FRC dithering consists of several components. Initially, the incoming 8-bit data is expanded to 9-bit data. This allows
the effective dithered result to support a total of 16.7 million colors. The incoming 9-bit data is evaluated, and one of four possible
algorithms is selected. The majority of incoming data sequences are supported by the default dithering algorithm. Certain incoming
data patterns (black/white pixel, full on/off sub-pixel) require special algorithms designed to eliminate visual artifacts associated
with these specific gray level transitions. Three algorithms are defined to support these critical transitions.
An example of the default dithering algorithm is illustrated in Figure 21. The “1” or “0” value shown in the table describes whether
the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated LSBs are “001”.
FIGURE 21. Default FRC Algorithm
30143473
See Table 11 for recommended FRC settings dependant on 18/24–bit source, 18/24–bit white balance LUT, and 18/24–bit display.
TABLE 11. Recommended FRC settings
Source
White Balance LUT
24–bit
24–bit
24–bit
24–bit
24–bit
18–bit
18–bit
24–bit
18–bit
24–bit
18–bit
18–bit
Display
24–bit
18–bit
18–bit
24–bit
18–bit
18–bit
FRC1
Disabled
Disabled
Enabled
Disabled
Disabled
Disabled
FRC2
Disabled
Enabled
Disabled
Disabled
Enabled
Disabled
Copyright © 1999-2012, Texas Instruments Incorporated
49