DS90UB926Q Datasheet, PDF (43/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
ADD
(dec)
44
ADD Register
(hex) Name
0x2C SSCG
Control
58 0x3A I2S MCLK
Output
65 0x41 Link Error
Count
Bit(s)
7:4
3
2:0
7
6:4
3:0
7:5
4
3:0
Register
Type
RW
RW
RW
RW
RW
RW
Default Function
(hex)
0x00
SSCG
Enable
SSCG
Selection
0x00
MCLK
Override
MCLK
Frequency
Slect
0x03
Link Error
Count
Enable
Link Error
Count
Descriptions
Reserved
Enable Spread Spectrum Clock Generator
0: Disable
1: Enable
SSCG Frequency Deviation:
When LFMODE = H
fdev fmod
000: +/- 0.7 CLK/628
001: +/- 1.3
010: +/- 1.8
011: +/- 2.5
100: +/- 0.7 CLK/388
101: +/- 1.2
110: +/- 2.0
111: +/- 2.5
When LFMODE = L
fdev fmod
000: +/- 0.9 CLK/2168
001: +/- 1.2
010: +/- 1.9
011: +/- 2.5
100: +/- 0.7 CLK/1300
101: +/- 1.3
110: +/- 2.0
111: +/- 2.5
1: Override divider select for MCLK
0: No override for MCLK divider
See Table 5
Reserved
Reserved
Enable serial link data integrity error count
1: Enable error count
0: Disable
Link error count threshold.
Counter is pixel clock based. clk0, clk1 and DCA are
monitored for link errors, if error count is enabled,
deserializer loose lock once error count reaches
threshold. If disabled deserilizer loose lock with one
error.
Copyright © 1999-2012, Texas Instruments Incorporated
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