DS90UB926Q Datasheet, PDF (30/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
Serial Control Bus
The DS90UB926Q is configured by the use of a serial control bus that is I2C protocol compatible. . Multiple deserializer devices
may share the serial control bus since 16 device addresses are supported. Device address is set via R₁ and R₂ values on IDx pin.
See Figure 19 below.
The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input / Output. The SDA is
the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to V_DD33. For most appli-
cations a 4.7 k pull-up resistor to V_DD33 may be used. The resistor value may be adjusted for capacitive loading and data rate
requirements. The signals are either pulled High, or driven Low.
FIGURE 19. Serial Control Bus Connection
30143401
The configuration pin is the IDx pin. This pin sets one of 16 possible device addresses. A pull-up resistor and a pull-down resistor
of suggested values may be used to set the voltage ratio of the IDx input (V_R2) and V_DD33 to select one of the other 16 possible
addresses. See Table 8.
TABLE 8. Serial Control Bus Addresses for IDx
Ideal Ratio
#
V_R2 / V_DD33
1
0
2
0.121
3
0.152
4
0.182
5
0.212
6
0.242
7
0.273
8
0.310
9
0.356
10
0.402
11
0.447
12
0.492
13
0.538
14
0.583
15
0.629
16
0.727
Ideal V_R2
(V)
0
0.399
0.502
0.601
0.700
0.799
0.901
1.023
1.175
1.327
1.475
1.624
1.775
1.924
2.076
2.399
Suggested
Resistor R1 kΩ
(1% tol)
Open
294
280
270
267
240
243
226
210
196
182
169
154
137
124
90.9
Suggested
Resistor R2 kΩ
(1% tol)
40.2 or Any
40.2
49.9
60.4
71.5
76.8
90.9
102
115
130
147
165
180
191
210
243
Address 7'b
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
Address 8'b
Appended
0x58
0x5A
0x5C
0x5E
0x60
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
30
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