DS90UB926Q Datasheet, PDF (19/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
INPUT EQUALIZATION GAIN
FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces the medium-induced
deterministic jitter. It equalizes up to 10m STP cables with 3 connection breaks at maximum serialized stream payload rate of 2.975
Gbps.
COMMON MODE FILTER PIN (CMF)
The deserializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional
common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability.
A 0.1 μF capacitor has to be connected to this pin to Ground.
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the
transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no
restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual
display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See
Figure 11.
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FIGURE 11. Video Control Signal Filter Waveform
EMI REDUCTION FEATURES
Spread Spectrum Clock Generation (SSCG)
The DS90UB926Q provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2.5% (5% total) at up to 100 kHz modulations
are available. This feature may be controlled by register. See Table 1, Table 2, and Table 9.
FIGURE 12. SSCG Waveform
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