DS90UB926Q Datasheet, PDF (22/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
CONFIGURATION SELECT (MODE_SEL)
Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and
a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (V_R4) and V_DD33 to select
one of the other 10 possible selected modes. See Figure 13 and Table 4.
30143441
FIGURE 13. MODE_SEL Connection Diagram
TABLE 4. Configuration Select (MODE_SEL)
# Ideal Ratio
V_R4/V_DD33
Ideal V_R4
(V)
Suggested
Resistor R3
kΩ (1% tol)
Suggested
Resistor R4
kΩ (1% tol)
LFMODE
Repeater
Backward
Compatible
I2S Channel
B
(18–bit
Mode)
1
0
0
Open
40.2 or Any
L
L
L
L
2
0.121
0.399
294
40.2
L
L
L
H
3
0.152
0.502
280
49.9
L
H
L
L
4
0.242
0.799
240
76.8
L
H
L
H
5
0.311
1.026
226
102
H
L
L
L
6
0.402
1.327
196
130
H
L
L
H
7
0.492
1.624
169
165
H
H
L
L
8
0.583
1.924
137
191
H
H
L
H
9
0.629
2.076
124
210
L
L
H
L
LFMODE: L = 15 – 85 MHz (Default); H = 5 – <15 MHz
Repeater: L = Repeater Off (Default); H = Repeater On
Backward Compatible: L = Backward Compatible Off (Default); H = Backward Compatible On to 905/907 (15 - 65MHz)
I2S Channel B: L = I2S Channel B Off, Normal 24-bit RGB Mode (Default); H = I2S Channel B On, 18-bit RGB Mode with I2S_DB
Enabled.
I2S RECEIVING
In normal 24-bit RGB operation mode, the DS90UB926Q provides up to 3-bit of I2S. They are I2S_CLK, I2S_WC and I2S_DA, as
well as the Master I2S Clock (MCLK). The audio is received through the forward video frame, or can be configured to receive during
video blanking periods. A jitter cleaning feature reduces I2S_CLK output jitter to +/- 2ns.
I2S Jitter Cleaning
The DS90UB926Q features a standalone PLL to clean the I2S data jitter supporting high end car audio systems. If I2S CLK
frequency is less than 1MHz, this feature has to be disabled through the register bit I2S Control (0x2B) in Table 9.
Secondary I2S Channel
In 18-bit RGB operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio channel in additional to
the 3–bit of I2S. The I2S_DB is synchronized to the I2S_CLK. To enable this synchronization feature on this bit, set the MODE_SEL
(Table 4) or program through the register bit (Table 9).
MCLK
The deserializer has an I2S Master Clock Output. It supports x1, x2, or x4 of I2S CLK Frequency. When the I2S PLL is disabled,
the MCLK output is off. below covers the range of I2S sample rates and MCLK frequencies.
By default, all the MCLK output frequencies are x2 of the I2S CLK frequencies. The MCLK frequencies can also be enabled through
the register bit [7:4] (I2S MCLK Output) of 0x3A shown in Table 9. To select desired MCLK frequency, write bit 7 (0x3A) = 1, then
write to bit [6:4] accordingly.
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