DS90UB926Q Datasheet, PDF (10/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2, Note 3, Note 4)
Symbol
Parameter
Conditions
Pin/Freq. Min Typ Max
GPIO BIT RATE
Forward Channel Bit Rate
B_R
Back Channel Bit Rate
(Note 8, Note 9)
f=5–
85MHz,
GPIO[3:0]
0.25*f
>50 >75
CML MONITOR DRIVER OUTPUT AC SPECIFICATIONS
Differential Output Eye Opening
E_W
Width
(Note 6)
R_L = 100Ω,
Jitter Freq >f / 40
CMLOUTP,
0.3
0.4
CMLOUTN,
E_H
Differential Output Eye Height ^{Figure 2 (Note 8, Note 9)}
f = 85MHz
200 300
SWITCHING CHARACTERISTICS
t_RCP
PCLK Output Period
t_RCP = t_TCP
t_RDC
PCLK Output Duty Cycle
LVCMOS Low-to-High
t_CLH
Transition Time
Figure 3
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
LVCMOS High-to-Low
t_CHL
Transition Time
Figure 3
V_DDIO = 1.71 - 1.89V,
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
Data Valid before PCLK – Setup ^VDDIO ^{= 1.71 - 1.89V,}
t_ROS
Time
SSCG = OFF
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
Figure 6
C_L = 12pF
Data Valid after PCLK – Hold ^VDDIO ^{= 1.71 - 1.89V,}
t_ROH
Time
SSCG = OFF
Figure 6
C_L = 12pF
V_DDIO = 3.0 – 3.6V,
C_L = 12pF
PCLK
11.76
T
200
45
50
55
2
3
2
3
ROUT[23:0],
HS, VS, DE,
2
3
PCLK,
LOCK,
PASS,
2
3
MCLK,
I2S_CLK,
2.2
I2S_WC,
I2S_DA,
2.2
I2S_DB
3.0
3.0
ROUT[23:0]
10
HS, VS, DE,
PCLK,
15
t_XZR
Active to OFF Delay
Figure 5 (Note 8, Note 9)
OEN = L, OSS_SEL = H
LOCK, PASS
MCLK,
I2S_CLK,
I2S_WC,
60
I2S_DA,
I2S_DB
t_DDLT
Lock Time
Figure 5 (Note 8, Note 9)
SSCG = OFF
f = 5 – 85MHz
5
40
t_DD
Delay – Latency
(Note 8, Note 9)
f = 5 – 85MHz
147*T
f = 5 – <15
0.5
MHz
t_DCCJ
Cycle-to-Cycle Jitter
(Note 8, Note 9)
SSCG = OFF
f = 15 – 85
0.2
MHz
I2S_CLK = 1
+/-2
- 12.28MHz
Units
Mbps
kbps
UI
mV
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
10
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