DS90UB926Q Datasheet, PDF (31/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
TABLE 9. Serial Control Bus Registers
ADD ADD Register
(dec) (hex) Name
Bit(s)
0 0x00 I2C Device ID 7:1
0
1 0x01 Reset
7
6:3
2
1
0
2 0x02 Configuration 7
[0]
6
5
4
3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default Function Descriptions
(hex)
Device ID 7–bit address of Deserializer
See Table 4
ID Setting
I2C ID Setting
1: Register I2C Device ID (Overrides IDx pin)
0: Device ID is from IDx pin
0x04
Remote Remote Auto Power Down
Auto Power 1: Power down when no forward channel link is
Down
detected
0: Do not power down when no forward channel link is
detected
Reserved
BC Enable Back channel enable
1: Enable
0: Disable
Digital
RESET1
Reset the entire digital block including registers
This bit is self-clearing.
1: Reset
0: Normal operation
Digital
RESET0
Reset the entire digital block except registers
This bit is self-clearing
1: Reset
0: Normal operation
0x00 Output
Enable
LVCMOS Output Enable.
1: Enable
0: Disable. Tri-state Outputs
OEN and
OSS_SEL
Override
Overrides Output Enable Pin and Output State pin
1: Enable override
0: Disable - no override
OSC Clock
Enable
OSC Clock Output Enable
If loss of lock OSC clock is output onto PCLK
0: Disable
1: Enable
Output
OSS Select to Control Output State during Lock Low
Sleep State Period
Select
1: Enable
(OSS_SEL) 0: Disable
Backward Mode_Sel Backward compatible Mode Override
Compatible Enable.
Mode
1: Use register bit "reg_02[2]" to set BC Mode
Override 0: Use MODE_SEL option.
Backward Backward Compatible Mode Select to DS90UR905Q
Compatible and DS90UR907Q. If Reg_02[3] = 1
Mode
1: Backward Compatible is on
Select
0: Backward Compatible is off
LFMODE
Pin
Override
LFMODE Pin Override Enable
1: Use register bit "reg_02[0]" to set LFMODE
0: Use LFMODE Pin
LFMODE
Low Frequency Mode Select
1: PCLK = 5 - <15 MHz
0: PCLK = 15 - 85 MHz
Copyright © 1999-2012, Texas Instruments Incorporated
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