DS90UB926Q Datasheet, PDF (18/57 Pages) Texas Instruments – 5 - 85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel

DS90UB926Q
Functional Description
The DS90UB926Q deserializer receives a 35-bits symbol over a single serial FPD-Link III pair operating upto 2.975 Gbps application
payload. The serial stream contains an embedded clock, video control signals and the DC-balanced video data and audio data
which enhance signal quality to support AC coupling.
The DS90UB926Q deserializer attains lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer regardless of the data pattern,
delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need of special training
patterns or sync characters. The deserializer recovers the clock and data by extracting the embedded clock information, validating
then deserializing the incoming data stream. The recovered parallel LVCMOS video bus is then provided to the display. The
deserializer is intended for use with the DS90UB925Q serializer, but is also backward compatible with DS90UR905Q or
DS90UR907Q FPD-Link II serializer.
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing DIN[23:0] or RGB[7:0] or YUV data, sync
signals, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 10 illustrates the serial stream per PCLK cycle. This
data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.
FIGURE 10. FPD-Link III Serial Stream
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The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps
minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Backward Channel (LS_BC) of the DS90UB926Q provides bidirectional communication between the display and
host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control
data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock
information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back
channel contains the I2C, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.
BACKWARD COMPATIBLE MODE
The DS90UB926Q is also backward compatible to DS90UR905Q and DS90UR907Q FPD Link II serializers at 15 - 65 MHz pixel
clock frequencies. It receives 28-bits of data over a single serial FPD-Link II pair operating at the line rate of 420 Mbps to 1.82
Gbps. This backward compatible mode is provided through the MODE_SEL pin (Table 4) or the configuration register (Table 9).
Note: In this mode, the minimum PCLK frequency is 15 MHz.
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