DS90UA102-Q1 Datasheet, PDF (4/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
DS90UA102-Q1 Pin Diagram
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RES0 37
CMLOUTP 38
CMLOUTN 39
VDDCML 40
RIN+ 41
RIN- 42
RES0 43
RES0 44
VDDPLL 45
RES0 46
PASS 47
LOCK 48
DS90UA102-Q1
DAP = GND
24 GPO3
23 GPO2
22 _GPO1
21 _GPO0
20 _VDDIO
19 _DOUT7
18 _DOUT6
17 VDDD
16 ^DOUT5
15 DOUT4
14 DOUT3
13 DOUT2
Figure 3. DS90UA102-Q1 — Top View
Pin Descriptions
Pin Name
Pin #
I/O, Type
Description
Digital Audio Interface
SCK
8
Output, LVCMOS System clock output.
Recovered system clock fed into the Serializer's SCK pin.
LRCK
9
Output, LVCMOS Word clock output.
BCK
10
Output, LVCMOS Bit clock output.
DOUT[7:0] 11, 12, 13, 14,
15, 16, 18, 19
Outputs,
LVCMOS
Digital audio data outputs.
LVCMOS Parallel Interface
GPIO[3:0]
28, 27, 26, 25 Inputs/Outputs, General purpose I/Os.
LVCMOS w/ pull May be configured as inputs to the back-channel (which can be read by the Serializer),
down
or as local register outputs.
GPO[3:0] 24, 23, 22, 21
Outputs,
LVCMOS
General purpose outputs, transported over the forward channel from the Serializer.
Control and Configuration
SDA
1
SCL
2
Input/Output,
Open Drain
Input/Output,
Open Drain
I²C data input/output line.
Must have an external pull-up to V_DDIO. DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
I²C clock line.
Must have an external pull-up to V_DDIO. DO NOT FLOAT.
Recommended pull-up: 4.7 kΩ.
OSS_SEL
4
Input, LVCMOS Output sleep state select. Refer to Table 5.
w/ pull down
4
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