DS90UA102-Q1 Datasheet, PDF (34/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
SCK
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ROUT
TRFB: 0
TRFB: 1
Figure 25. Programmable SCK Strobe Select
Built In Self Test (BIST)
An optional at-speed built in self test (BIST) feature supports the testing of the high speed serial link and low-
speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also for
system diagnostics.
BIST Configuration and Status
The DS90UA101-Q1/DS90UA102-Q1 chipset can be programmed into BIST mode using either pins or registers.
By default BIST configuration is controlled through pins on the DS90UA102-Q1. BIST can be configured via
registers using BIST Control Register 0x24, also on the DS90UA102-Q1. Pin based configuration is defined as
follows:
• BISTEN (on DS90UA102-Q1) = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.
• GPIO3 and GPIO2 of DS90UA102-Q1: Defines the BIST clock source (SCK vs. various internal oscillator
frequencies). See Table 3 below.
Table 3. BIST Pin Configuration on DS90UA102-Q1 Deserializer⁽¹⁾
DS90UA102-Q1 Deserializer GPIO[3:2]
00
01
10
11
Oscillator Source
External
Internal
Internal
Internal
BIST Frequency (MHz)
SCK
~25
~50
~12.5
(1) Note: These pin settings will only be active when 0x24[3] = 1 and BIST is on.
The BIST mode provides various options for the clock source. Either external pins (GPIO3 and GPIO2 of DES)
or register 0x24 on DES can be used to configure the BIST to use SCK or various internal oscillator frequencies
as the clock source. Refer to Table 4 below for BIST register settings.
Table 4. BIST Register Configuration on DS90UA102-Q1 Deserializer⁽¹⁾
DS90UA102-Q1 Deserializer 0x24[2:1]
00
01
10
11
Oscillator Source
External
Internal
Internal
Internal
BIST Frequency (MHz)
SCK
~50
~25
~12.5
(1) Note: These register settings will only be active when 0x24[3] = 0 and BIST is on.
The BIST status can be monitored real time on the PASS pin. For every frame with error(s), the PASS pin
toggles low momentarily. If two consecutive frames have errors, PASS will toggle twice to allow counting of
frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status momentarily (pass = no
errors, fail = one or more errors). The BIST result can also be read through I²C for the number of frames that
errored. The status register retains results until it is reset by a new BIST session or a device reset. For all
practical purposes, the BIST status can be monitored from the BIST Error Count Register 0x25 on the
DS90UA102-Q1 Deserializer.
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