DS90UA102-Q1 Datasheet, PDF (33/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
www.ti.com
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
NOTE
Note: The alias ID must be set in order to communicate with any remote device. For
example:
• When there is only one SER/DES pair and no remote slaves: if I²C Master on the DES
side wants to communicate with the remote SER, I²C pass-through must be enabled
on the DES and the SER Alias ID must also be set before the I²C Master can
communicate with the remote SER (the SER ID is automatically configured by default if
there is LOCK).
• When there is only one SER/DES pair and one remote slave connected to the SER: if
I²C Master on the DES side (with pass-through enabled) wants to communicate with
the remote slave, the Slave ID and Slave Alias ID must be set before the I²C Master
can communicate with the remote slave, even if there is only one remote slave.
Slave Clock Stretching
To communicate and synchronize with remote devices on the I²C bus through the Bidirectional Control Channel,
the chipset utilizes bus clock stretching (holding the SCL line low) during data transmission. On the 9th clock of
every I²C transfer (before the ACK signal), the local I²C slave pulls the SCL line low until a response is received
from the remote I²C bus located on the other end of the serial interface. The slave device will not control the
clock and only stretches it until the remote peripheral has responded. The I²C Master must support slave clock
stretching in order to communicate with remote devices.
General Purpose Inputs, Outputs (GPIs, GPOs, GPIOs) Descriptions
There are 4 dedicated general purpose inputs (GPIs) on the DS90UA101-Q1 and 4 dedicated general purpose
outputs (GPOs) on the DS90UA102-Q1. Inputs to the GPI pins on the Serializer are fed to the GPO outputs on
the Deserializer. The maximum GPI data rate is defined by the SCK source (up to 50 Mbps).
In addition, there are also 4 GPOs on the DS90UA101-Q1 and 4 GPIOs on the DS90UA102-Q1. The GPOs on
the Serializer can be configured as outputs for the input signals that are fed into the Deserializer GPIOs. The
GPIO maximum data rate is up to 66 kbps when configured for communication between Deserializer GPIO to
Serializer GPO. Both the GPOs on the Serializer and GPIOs on the Deserializer can also behave as outputs
whose values are set from local registers.
LVCMOS V_DDIO Option
1.8V/3.3V Deserializer outputs are user configurable to provide compatibility with 1.8V and 3.3V system
interfaces.
Power Up Requirements and PDB Pin
The Deserializer is active when the PDB pin is driven HIGH. Driving the PDB pin LOW powers down the device
and clears all control register configurations to default values. The PDB pin must be held low until the power
supplies (V_DDn and V_DDIO) have settled to the recommended operating voltage. This can be done by driving PDB
externally, or an external RC network can be connected to the PDB pin to ensure PDB arrives after all the power
supplies have stabilized.
Powerdown
The PDB pin's function on the Deserializer is to ENABLE or powerdown the device. This pin can be controlled by
the system and can be used to disable the DES to save power. When PDB = HIGH, the DES will lock to the
input stream and assert the LOCK pin (HIGH) and output valid data. When PDB = LOW, all outputs are in TRI-
STATE.
SCK Clock Edge Select (RRFB)
The RRFB selects which edge of the output clock that the data is strobed on. If RRFB register is 1, data is
strobed on the rising edge of SCK. If RRFB register is 0, data is strobed on the falling edge of SCK.
Copyright © 2013, Texas Instruments Incorporated
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