DS90UA102-Q1 Datasheet, PDF (25/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
www.ti.com
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
FUNCTIONAL DESCRIPTION
The DS90UA101-Q1/DS90UA102-Q1 chipset is intended to link digital audio sources with remote audio
converters and DSPs. The chipset can operate from a reference clock of 10MHz to 50MHz. The DS90UA101-Q1
device serializes up to an 8 audio inputs and 4 general purpose inputs, along with a bidirectional control channel,
into a single high-speed differential pair or single-ended coaxial cable. The high speed serial bit stream contains
an embedded clock and DC-balanced information to enhance signal quality and support AC coupling. The
DS90UA102-Q1 device receives the single serial data stream and converts it back to digital audio outputs,
control channel data, and general purpose outputs (GPOs). The DS90UA101-Q1/DS90UA102-Q1 chipset can
accept up to 8 audio data inputs, bit clock (BCK), word clock (LRCK), and an input reference clock (SCK) ranging
from 10 MHz to 50 MHz.
The control channel function of the chipset provides bidirectional communication between the two ends of the
link, such as a digital signal processor (DSP) on one end and an audio digital-analog converter (DAC) on the
other. The integrated Bidirectional Control Channel transfers data bidirectionally over the same differential pair
used for audio data interface. This interface offers advantages over other chipsets by eliminating the need for
additional wires for programming and control. The Bidirectional Control Channel bus is controlled via an I²C port,
available on both the Serializer and Deserializer.
Transmission Media
The DS90UA101-Q1/DS90UA102-Q1 chipset is intended to be used in a point-to-point data link through a
shielded twisted pair (STP) or coaxial (coax) cable. The Serializer and Deserializer provide internal termination to
minimize impedance discontinuities. The interconnect (cable and connectors) should have a differential
impedance of 100Ω, or a single-ended impedance of 50Ω. The maximum length of cable that can be used is
dependent on the quality of the cable (gauge, impedance), connector, board (discontinuities, power plane), and
the electrical environment (for example, power stability, ground noise, input clock jitter, SCK frequency, etc). The
resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. This can be done by measuring the output of the CMLOUTP/N
pins. These pins should each be terminated with a 0.1 µF capacitor in series with a 50Ω resistor to GND. Figure
10 illustrates the minimum eye width and eye height that is necessary for bit error free operation.
Operation with Audio System Clock as Reference Clock
The DS90UA101-Q1/DS90UA102-Q1 chipset is operated using the audio system clock (SCK) from the digital
audio source. The audio data, LRCK, and BCK inputs are clocked into the Serializer using SCK. Up to 4 GPI
inputs are also sampled and transported along with the digital audio inputs. Figure 13 shows the operation of the
Serializer and Deserializer with the reference clock.
DSP
Serializer
DIN[7:0]
LRCK
BCK
SDA
SCL
GPI[3:0]
GPO[3:0]
SCK
PLL
Forward Channel
DOUT+
RIN+
DOUT-
RIN-
Bidirectional
Control Channel
Deserializer
DOUT[7:0]
LRCK
BCK
SCK
GPO[3:0]
GPIO[3:0]
SDA
SCL
DAC
REF
Figure 13. Operation with SCK Reference
Copyright © 2013, Texas Instruments Incorporated
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