DS90UA102-Q1 Datasheet, PDF (23/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

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Addr
(Hex)
Name
Bits
Field
R/W
7 I²C Pass All
RW
0x21
I²C Control 1
6:4 I²C SDA Hold Time RW
3:0 I²C Filter Depth
RW
7
Forward Channel
Sequence Error
R
6
Clear Sequence
Error
RW
5 RSVD
4:3 SDA Output Delay RW
0x22
I²C Control 2
2 Local Write Disable RW
1
I²C Bus Timer
Speedup
RW
0
I²C Bus Timer
Disable
RW
0x23
General Purpose
Control
7:0 GPCR[7:0]
RW
DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Default (Hex)
0x17
0x00
0x00
Description
Pass-through all I²C transactions. For an
explanation of I²C pass-through, refer to I²C
Pass-Through and Multiple Device Addressing.
1: Enable pass-through of all I²C accesses to
I²C IDs that do not match the Deserializer I²C
ID. The I²C accesses are then remapped to the
address specified in register 0x06.
0: Enable pass-through only of I²C accesses to
I²C IDs matching either the remote Serializer
I²C ID or the remote slave I²C ID.
Internal SDA hold time. This field configures the
amount of internal hold time provided for the
SDA input relative to the SCL input. Units are
50ns.
I²C glitch filter depth. This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
Control channel sequence error detector. This
bit indicates a sequence error has been
detected in the forward control channel.
1: At least one error has occurred in the
forward control channel.
0: No errors have been detected in the forward
control channel.
Clears the Forward Channel Sequence Error
bit.
Reserved.
SDA output delay. This field configures the
output delay on the SDA output. Setting this
value will increase the output delay in units of
50 ns. Nominal output delay values for SCL to
SDA are:
00: 350 ns
01: 400 ns
10: 450 ns
11: 500 ns
Disable remote writes to local registers. Setting
this bit to 1 will prevent remote writes to local
device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I²C Master
attached to the Serializer. Setting this bit does
not affect remote access to I²C slaves at the
Deserializer.
Speed up I²C bus Watchdog Timer.
1: Watchdog Timer expires after approximately
50 microseconds.
0: Watchdog Timer expires after approximately
1 second.
The I²C Watchdog Timer may be used to
detect when the I²C bus is free or hung up
following an invalid termination of a transaction.
If SDA is high and no signaling occurs for
approximately 1 second, the I²C bus is
assumed to be free. If SDA is low and no
signaling occurs, the device will attempt to clear
the bus by driving 9 clocks on SCL.
1: Disable the I²C bus Watchdog Timer.
0: Enable the I²C bus Watchdog Timer.
Scratch Register. Used to write and read 8 bits.
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