DS90UA102-Q1 Datasheet, PDF (26/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
www.ti.com
The Serializer switches over to an internal reference clock when SCK is idle or missing. This frequency is
selectable via the device control registers, as shown below (Table 1).
Table 1. Internal Oscillator Frequencies for Forward Channel Frame during Normal Operation
DS90UA101-Q1
Reg 0x14 [2:1]
00
01
10
11
Frequency (MHz)
~25
~50
~25
~12.5
Line Rate Calculations for the DS90UA101-Q1/DS90UA102-Q1
The following formula is used to calculate the line rate for the DS90UA101-Q1/DS90UA102-Q1 chipset:
• Line rate = ƒ_SCK * 28
For example, for maximum line rate, ƒ_SCK= 50 MHz, line rate = 50 * 28 = 1.4 Gbps.
Serial Frame Format
The high speed forward channel is composed of 28 bits of data containing digital audio data, sync signals, I²C
and parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is
randomized, balanced and scrambled. The Bidirectional Control Channel data is transferred over the single serial
link along with the high-speed forward data. This architecture provides a full duplex, low speed control path
across the serial link together with the high speed forward channel.
Serial Audio Formats
There are several de-facto industry standards or formats that define the required alignments and signal polarities
between the left/right clock (LRCK), bit clock (BCK) and the serial audio data. Hence, this section is dedicated to
discussing various serial audio formats.
I²S Format
An I²S bus uses three signal lines for data transfer – a frame or word clock (LRCK), a bit clock (BCK), and a
single or multiple data lines. The device which generates the appropriate BCK and LRCK signals on the bus is
called Master, whereas other devices which accept BCK and LRCK as inputs are all slaves.
Bit Clock (BCK)
The bit clock pulses once for each discrete bit of data on the data lines. The bit clock frequency must be greater
than or equal to the product of the sample rate, the number of bits per sample and the number of channels
(which is 2 in normal stereo operation).
Word Select (LRCK)
The word select line indicates the channel being transmitted:
• LRCK = 0; channel 1 (left);
• LRCK = 1; channel 2 (right).
The LRCK line changes one clock period before the MSB is transmitted (Figure 14). This allows the slave
transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it
enables the receiver to store the previous word and clear the input for the next word.
Serial Data (DATA)
Serial data is transmitted in two’s complement with the MSB first (as shown in Figure 14). The MSB is
transmitted first because the transmitter and receiver may have different word lengths.
If the receiver is sent more bits than its word length, the bits after the LSB are ignored. On the other hand, if the
receiver is sent fewer bits than its word length, the missing bits are set to zero internally. And so, the MSB has a
fixed position, whereas the position of the LSB depends on the word length.
26
Submit Documentation Feedback
Product Folder Links: DS90UA102-Q1
Copyright © 2013, Texas Instruments Incorporated