DS90UA102-Q1 Datasheet, PDF (29/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
www.ti.com
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the
forward channel, the PASS pin will go low momentarily.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
Bidirectional Control Bus and I²C
The I²C compatible interface allows programming of the Serializer, Deserializer, or an external remote device
through the Bidirectional Control Channel. For example, an audio module connected to the Deserializer can
communicate with the ADC connected to the Serializer using the Bidirectional Control Channel. Register
programming transactions to/from the chipset are employed through the clock (SCL) and data (SDA) lines. These
two signals have open drain I/Os and both lines must be pulled-up to V_DDIO by an external resistor. Pull-up
resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being
driven low. A logic LOW is transmitted by driving the output low. Logic HIGH is transmitted by releasing the
output and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the
total bus capacitance and operating speed. The DS90UA101-Q1/DS90UA102-Q1 I²C bus data rate supports up
to 400 kbps according to I²C fast mode specifications. Figure 18, Figure 19, Figure 20, Figure 21 show I²C
waveforms of read/write bytes, basic operation, and start/stop conditions.
N
Bus Activity:
A
Master
Slave
Register
Slave
C
Address
Address
Address
K
SDA Line S
7-bit Address 0
S
7-bit Address 1
P
Bus Activity:
Slave
A
A
C
C
K
K
Figure 18. Read Byte
A
Data
C
K
Bus Activity:
Master
SDA Line S
Slave
Address
7-bit Address 0
Register
Address
Data
P
Bus Activity:
Slave
A
A
A
C
C
C
K
K
K
Figure 19. Write Byte
SDA
SCL
START
MSB
1
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
Figure 20. Basic Operation
STOP
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: DS90UA102-Q1
Submit Documentation Feedback
29