DS90UA102-Q1 Datasheet, PDF (24/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Addr
(Hex)
Name
Bits
Field
7:4 RSVD
3
BIST Pin
Configuration
0x24
BIST Control
2:1 BIST Clock Source
R/W
RW
RW
0 BIST Enable
RW
0x25 Parity Error Count 7:0 BIST Error Count
R
0x3F
CML Output
Enable
7:5 RSVD
4 CML OUT Enable
RW
3:0 RSVD
0x40 SCL High Time 7:0 SCL High Time
RW
0x41
SCL Low Time
7:0 SCL Low Time
RW
7:2 RSVD
1
Force Back
Channel Error
RW
0x42 CRC Force Error
Force One Back
0 ^{Channel Error}
RW
0x4D AEQ Test Mode
7 RSVD
Select
6 ^{AEQ Bypass}
RW
0x4E EQ Value
5:0 RSVD
7:0
AEQ / Manual Eq
Readback
R
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Default (Hex)
0x08
0x00
0x10
0x82
0x82
0x00
0x20
Description
Reserved.
BIST configuration select:
1: BIST configured through pin.
0: BIST configured through register bit 0x24[0].
BIST clock source:
See (Table 1)
BIST register enable (active if 0x24[3] is set to
0):
1: Enabled.
0: Disabled.
Number of forward channel parity errors during
the BIST.
Reserved.
1: CML loop-through driver is powered down.
0: CML loop-through driver is powered up.
Reserved.
I²C Master SCL high time. This field configures
the high pulse width of the SCL output when
the Deserializer is the Master on the local I²C
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
satisfy a minimum (4 μs + 0.3 μs of rise time for
cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26 MHz rather than the nominal 20 MHz.
I²C Master SCL low time. This field configures
the low pulse width of the SCL output when the
Deserializer is the Master on the local I²C bus.
This value is also used as the SDA setup time
by the I²C slave for providing data prior to
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to satisfy a minimum (4.7 µs
+ 0.3 µs of fall time for cases where fall time is
very fast) SCL low time with the internal
oscillator clock running at 26 MHz rather than
the nominal 20 MHz.
Reserved.
1: This bit introduces multiple errors into the
back channel frame.
0: No effect.
1: This bit introduces ONLY one error into the
back channel frame. This bit is also self
clearing.
0: No effect.
Reserved.
Bypass AEQ and use manual EQ. Set value
using register 0x04.
Reserved.
Read back the equalization value (adaptive or
manual).
24
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