DS90UA102-Q1 Datasheet, PDF (35/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
www.ti.com
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Sample BIST Sequence (Refer to Figure 26)
Step 1: BIST mode is enabled via the BISTEN pin on the DS90UA102-Q1 Deserializer, or through the
Deserializer control registers. The clock source is selected through the GPIO3 and GPIO2 pins as shown in
Table 3.
Step 2: The DS90UA101-Q1 Serializer BIST start command is activated through the back channel.
Step 3: The BIST pattern is generated and sent through the serial interface to the Deserializer. Once the
Serializer and Deserializer are in the BIST mode and the Deserializer acquires LOCK, the PASS pin of the
Deserializer goes high and BIST starts checking the data stream. If an error in the payload is detected the PASS
pin will switch low momentarily. During the BIST test, the PASS output can be monitored and counted to
determine the payload error rate.
Step 4: To stop the BIST mode, the Deserializer BISTEN pin is set low and the Deserializer stops checking the
data. The final test result is not maintained on the PASS pin. To check the number of BIST errors, check the
BIST Error Count register, 0x25 on the Deserializer. The link returns to normal operation after the Deserializer
BISTEN pin is low.
Figure 27 below shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and
Case 2 shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of
the link (differential data transmission, adaptive equalization, etc.), thus they may be introduced by greatly
extending the cable length, increasing the frequency, or by reducing signal condition enhancements (Rx
equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in
BIST
BIST
start
Step 3: SER/DES in
BIST ± monitor
PASS
BIST
stop
Step 4: DES/SER in
Normal, check register
0x25 on DES
Figure 26. AT-Speed BIST System Flow Diagram
BISTEN
(DES)
LOCK
SCK
(RFB = L)
DOUT[7:0]
SSO
DATA
(internal)
PASS
Prior Result
PASS
DATA
X
(internal)
PASS
Prior Result
X = bit error(s)
X
X
FAIL
Normal
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 27. BIST Timing Diagram
Copyright © 2013, Texas Instruments Incorporated
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