DS90UA102-Q1 Datasheet, PDF (27/46 Pages) Texas Instruments – DS90UA102-Q1 Multi-Channel Digital Audio Link

DS90UA102-Q1
www.ti.com
SNLS442A – JULY 2013 – REVISED SEPTEMBER 2013
Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading
(LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the
leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is
synchronized with the leading edge.
LRCK
LEFT Channel Data
RIGHT Channel Data
BCK
DIN
MSB
210
LSB
MSB
Figure 14. Stereo I²S Format
210
LSB
Left Justified Format
In this format, MSB of the word appears in synchronization with the LRCK edges. Unlike in I²S mode, there is no
lag between Data and LRCK. Left channel data word begins at falling edge of LRCK and right channel data word
begins on rising edge of the LRCK signal. Hence, as can be seen from below waveforms (Figure 15), data
appears to be left justified.
LRCK
RIGHT Channel Data
LEFT Channel Data
BCK
DIN
MSB
210
LSB
MSB
Figure 15. Left-Justified Format
210
N
LSB
Right Justified Format
In this format, LSB of the word appears just before the LRCK edges. Left channel data word may begin at any
point depending upon the word length, but LSB of this data word must appear just before the rising edge of the
LRCK signal. Similarly, LSB of the right channel data word must appear just before falling edge of the LRCK
signal. Hence, as can be seen from below waveforms(Figure 16), data appears to be right justified.
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