DS80PCI102_15 Datasheet, PDF (4/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
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Pin Functions^(1)(2)(3)(4) (continued)
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
ENSMB = 1 (SMBus SLAVE MODE)
SCL
5
I, 2-LEVEL, In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or open drain output.
LVCMOS, O, External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface
open drain standards.⁽⁵⁾
SDA
4
I, 2-LEVEL, In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
LVCMOS, O, External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface
open drain standards.⁽⁵⁾
AD0-AD3
10, 9, 2, 1 I, 4-LEVEL,
LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus
slave address inputs.
External 1-kΩ pullup or pulldown recommended.
READEN
17
I, 2-LEVEL, When in SMBus Slave Mode the READEN pin must be tied LOW for the AD[3:0] to be
LVCMOS
active. If this pin is tied HIGH or FLOAT, the device slave address is 0xB0.
ENSMB = FLOAT (SMBus MASTER MODE)
I, 2-LEVEL, Clock output when loading EEPROM configuration, reverting to SMBus clock input when
SCL
5
LVCMOS, O, EEPROM load is complete (DONE = 0).
open drain External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface
standards. ⁽⁵⁾
SDA
I, 2-LEVEL, In both SMBus Modes, this pin is the SMBus data I/O. Data input or open drain output.
4
LVCMOS, O, External 2-kΩ to 5-kΩ pullup resistor to VDD or VIN recommended as per SMBus interface
open drain standards.⁽⁵⁾
AD0-AD3
READEN
I, 4-LEVEL,
10, 9, 2, 1 LVCMOS
I, 2-LEVEL,
17
LVCMOS
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the user set SMBus
slave address inputs.
External 1-kΩ pullup or pulldown recommended.
A logic low on this pin starts the load from the external EEPROM.⁽⁶⁾
Once EEPROM load is complete (DONE = 0), this pin functionality remains as READEN. It
does not revert to an SD_TH input.
DONE
O, 2-LEVEL, Valid register load status output
18
LVCMOS
HIGH = External EEPROM load failed or incomplete
LOW = External EEPROM load passed
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
I, 4-LEVEL,
LVCMOS
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins. The pins are active
only when ENSMB is deasserted (LOW).
When ENSMB goes high the SMBus registers provide independent control of each lane, and
the EQA[1:0] and EQB[1:0] pins are converted to SMBUS AD[3:0] inputs.
See Table 2.
DEMA, DEMB 4, 5
I, 4-LEVEL,
LVCMOS
DEMA DEMB controls the level of de-emphasis. The DEMA/B pins are only active when
ENSMB is deasserted (LOW). DEMA controls the A channel and DEMB controls the B
channel. When ENSMB goes high the SMBus registers provide independent control of each
channel and the DEM pins are converted to SMBUS SDA and SCL pins.
See Table 3.
CONTROL PINS — BOTH PIN AND SMBUS MODES (LVCMOS)
PRSNT
6
I, 2-LEVEL,
LVCMOS
Cable Present Detect input. High when a cable is not present per PCIe Cabling Spec. 1.0.
Puts part into low power mode. When LOW (normal operation) part is enabled.
See Table 4.
VOD_SEL
17
I, 4-LEVEL, VOD Select pin. See Table 3.
LVCMOS
VDD_SEL
16
I, LVCMOS
Controls the internal regulator.
FLOAT = 2.5-V mode
Tie GND = 3.3-V mode
See Figure 16.
RXDET
18
I, 4-LEVEL,
LVCMOS
The RXDET pin controls the receiver detect function. Depending on the input level, a 50-Ω or
> 50-kΩ termination to the power rail is enabled.
See Table 4.
(5) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5-V mode or 3.3-V mode.
(6) When READEN is asserted low, the device attempts to load EEPROM. If EEPROM cannot be loaded successfully, for example due to
an invalid or blank hex file, the DS80PCI102 waits indefinitely in an unknown state where SMBus access is not possible. DONE pin
remains high in this situation.
4
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