DS80PCI102_15 Datasheet, PDF (38/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
3.3-V or 2.5-V Supply Mode Operation (continued)
3.3 V mode
Enable
VDD_SEL
Internal
voltage
regulator
2.5 V
VIN
VDD
VDD
3.3 V
0.1 µF
0.1 µF
2.5 V mode
Disable
VDD_SEL
open
Internal
voltage
regulator
VIN
open
VDD
VDD
0.1 µF
0.1 µF
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2.5 V
Place 0.1 µF capacitors close to VDD Pins
Total capacitance should be % 0.2 µF
Place 0.1 µF capacitors close to VDD Pins
Figure 16. 3.3 V or 2.5 V Supply Connection Diagram
9.2 Power Supply Bypass
Two approaches are recommended to ensure that the DS80PCI102 is provided with an adequate power supply
bypass. First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent
layers of the printed circuit board. Second, careful attention to supply bypassing through the proper use of
bypass capacitors is required. A 0.1 μF bypass capacitor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the device. Small body size capacitors (such as 0402) reduce the
parasitic inductance of the capacitor and also help in placement close to the VDD pin. If possible, the layer
thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply
with distributed capacitance.
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