DS80PCI102_15 Datasheet, PDF (36/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
Typical Application (continued)
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Pattern
Generator
V_ID = 1.0 Vp-p,
DE = -9 dB
8 Gb/s, PRBS23
TL1
Lossy Channel
IN DS80PCI102 OUT
TL2
Lossy Channel
Figure 11. Test Setup Connections Diagram
Scope
BW = 50 GHz
8.2.1 Design Requirements
As with any high speed design, there are many factors which influence the overall performance. The following list
indicates critical areas for consideration during design.
• Use 100-Ω impedance traces. Length matching on the P and N traces should be done on the single-end
segments of the differential pair.
• Use uniform trace width and trace spacing for differential pairs.
• Place AC-coupling capacitors near to the receiver end of each channel segment to minimize reflections.
• For Gen3, AC-coupling capacitors of 220 nF are recommended, maximum body size is 0402, and add cutout
void on GND plane below the landing pad of the capacitor in order to reduce parasitic capacitance to GND.
• Back-drill connector vias and signal vias to minimize stub length.
• Use Reference plane vias to ensure a low inductance path for the return current.
8.2.2 Detailed Design Procedure
The DS80PCI102 should be placed at an offset location and close to the Rx with respect to the overall channel
attenuation. The suggested settings are recommended as a starting point for most applications. Once these
settings are configured, additional adjustments of the DS80PCI102 EQ or DE may be required to optimize the
repeater performance. The CTLE and DFE coefficient in the Rx can also be adjusted to further improve the eye
opening.
8.2.3 Application Curves
DS80PCI102 Settings:
EQ[1:0] = [R, R] or 0x15, Dem[1:0] = [Float, Float]
Figure 12. TL = 20-Inch 4–Mil FR4 Trace
DS80PCI102 Settings:
EQ[1:0] = [Float, R] or 0x1F, DEM[1:0] = [Float, Float]
Figure 13. TL = 35-Inch 4–Mil FR4 Trace
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