DS80PCI102_15 Datasheet, PDF (18/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
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– AD[3:0] = 0100'b, the device address byte is 0xB8
• The master implementation in the DS80PCI102 supports multiple devices reading from one EEPROM. When
tying multiple devices to the SDA and SCL pins, use these guidelines:
– Use adjacent SMBus addresses for the 4 devices
– Use a pullup resistor on SDA; value = 4.7 kΩ
– Use a pullup resistor on SCL; value = 4.7 kΩ
– Daisy-chain READEN (Pin 17) and DONE (Pin18) from one device to the next device in the sequence.
1. Tie READEN of the first device in the chain (U1) to GND
2. Tie DONE of U1 to READEN of U2
3. Tie DONE of U2 to READEN of U3
4. Tie DONE of U3 to READEN of U4
5. Optional: Tie DONE of U4 to a LED to show each of the devices have been loaded successfully
7.5.6.1 Master EEPROM Programming
The following example represents a 2 kbits (256 × 8-bit) EEPROM in hex format for the DS80PCI102 device. The
first 3 bytes of the EEPROM always contain a header common and necessary to control initialization of all
devices connected to the same SMBus line. There is a CRC enable flag to enable or disable CRC checking.
There is a MAP bit to flag the presence of an address map that specifies the configuration data start in the
EEPROM. If the MAP bit is not present, the configuration data start address immediately follows the 3-byte base
header. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the EEPROM. There are
37 bytes of data size for each DS80PCI102 device. For more details about EEPROM programming and Master
mode, refer to SNLA228.
1 :1000000000002000000407002FED4002FED4002FC4
2 :10001000AD4002FAD400005F568005F5A8005F5AE9
3 :100020008005F5A800005454F100000000000000A8
4 :1000300000000000000000000000000000000000C0
5 :1000400000000000000000000000000000000000B0
6 :1000500000000000000000000000000000000000A0
7 :100060000000000000000000000000000000000090
8 :100070000000000000000000000000000000000080
9 :100080000000000000000000000000000000000070
10 : 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0
11 : 1 0 0 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0
12 : 1 0 0 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0
13 : 1 0 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0
14 : 1 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0
15 : 1 0 0 0 E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
16 : 1 0 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
17 : 0 0 0 0 0 0 0 1 F F
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CRC-8 based on 40 bytes of
data in this shaded area
CRC Polynomial = 0x07
Insert the CRC value here
MAX EEPROM Burst = 32
Figure 8. Typical EEPROM Data Set
NOTE
The maximum EEPROM size supported is 8kbits (1024 × 8 bits).
The CRC-8 calculation is performed on the first 3 bytes of header information plus the 37 bytes of data for the
DS80PCI102, or 40 bytes in total. The result of this calculation is placed immediately after the DS80PCI102 data
in the EEPROM, which ends with "5454". The CRC-8 in the DS80PCI102 uses a polynomial = x⁸ + x² + x + 1.
There are two pins that provide unique functions in SMBus Master mode:
• DONE
• READEN
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