DS80PCI102_15 Datasheet, PDF (19/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

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DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
When the DS80PCI102 is powered up in SMBus master mode, it reads its configuration from the external
EEPROM when the READEN pin goes low. When the DS80PCI102 is finished reading its configuration from the
external EEPROM, it drives the DONE pin low. In applications where there is more than one DS80PCI102 on the
same SMBus, bus contention can result if more than one DS80PCI102 tries to take control of the SMBus at the
same time. The READEN and DONE pins prevent this bus contention. The system should be designed so that
the READEN pin from one DS80PCI102 in the system is driven low on power-up. This DS80PCI102 will take
command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is
finished reading its configuration, it will drive the DONE pin low. This pin should be connected to the READEN
pin of another DS80PCI102. When this second DS80PCI102 senses its READEN pin driven low, it will take
command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its
DONE pin low. By connecting the DONE pin of each DS80PCI102 to the READEN pin of the next DS80PCI102,
each DS80PCI102 can read its initial configuration from the EEPROM without causing bus contention.
EEPROM
GND
AD0
GND
AD1
GND
AD2
One or both of these lines
should float for EEPROM
larger than 256 bytes.
SDA
SCL
3.3V
Note: Set AD[3:0] of each DS80PCI102 to unique SMBus Address.
From External
SMBus Master
FLOAT
FLOAT
FLOAT
OUTA+ 7
OUTA- 8
AD1 9
AD0 10
INB+ 11
INB- 12
SMBUS AND
CONTROL
24 INA+ ^OUTA+ 7
23 INA- ^OUTA- 8
22 _VDD
AD1 9
21 _VDD
AD0 10
20 OUTB+ ^{INB+ 11}
19 OUTB- ^{INB- 12}
SMBUS AND
CONTROL
24 INA+ OUTA+ ₇
23 INA- OUTA- 8
22 _VDD
21 _VDD
AD1 9
AD0 10
20 OUTB+ INB+ 11
19 ^OUTB- INB- 12
SMBUS AND
CONTROL
24 INA+
23 INA-
22 _VDD
21 _VDD
20 OUTB+
19 OUTB-
Figure 9. Typical Multi-Device EEPROM Connection Diagram
7.5.6.2 EEPROM Address Mapping
A detailed EEPROM Address Mapping for a single device is shown in Table 7. For instances where multiple
devices are written to EEPROM, the device starting address definitions align starting with Byte 0x03. A register
map overview for a multi-device EEPROM address map is shown in Table 8.
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