DS80PCI102_15 Datasheet, PDF (3/46 Pages) Texas Instruments – 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 1-Lane PCI-Express Repeater With Equalization and De-Emphasis

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5 Pin Configuration and Functions
RTW Package
24 Pins
Top View
DS80PCI102
SNLS344G – JULY 2011 – REVISED AUGUST 2015
OUTA+ ₇
OUTA- 8
AD1/EQA1 9
AD0/EQA0 10
INB+ 11
INB- ₁₂
TOP VIEW
DAP = GND
24 INA+
23 INA-
22 VDD
21 VDD
20 OUTB+
19 OUTB-
PIN
NAME
NO.
I/O, TYPE
DIFFERENTIAL HIGH SPEED I/O'S
INA+, INA-,
INB+, INB-
24, 23
11, 12
I, CML
OUTA+, OUTA-, 7, 8
OUTB+, OUTB- 20, 19
O, CML
CONTROL PINS — SHARED (LVCMOS)
ENSMB
3
I, 4-LEVEL,
LVCMOS
Pin Functions^(1)(2)(3)(4)
DESCRIPTION
Inverting and noninverting differential inputs to the equalizer. A gated on-chip 50-Ω
termination resistor connects INn+ to VDD and INn- to VDD depending on the state of
RXDET. See Table 4
AC coupling required on high-speed I/O
Inverting and noninverting 50-Ω driver outputs with de-emphasis. Compatible with AC-
coupled CML inputs.
System management bus (SMBus) enable pin
Tie 1 kΩ to VDD (2.5-V mode) or VIN (3.3-V mode) = Register access SMBus slave mode
FLOAT = Read external EEPROM (master SMBUS mode)
Tie 1 kΩ to GND = Pin mode
(1) LVCMOS inputs without the “FLOAT” conditions must be driven to a logic low or high at all times or operation is not verified.
(2) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10% to 90%.
(3) For 3.3-V mode operation, VIN pin = 3.3 V and the VDD for the 4-level input is 3.3 V.
(4) For 2.5-V mode operation, VDD pin = 2.5 V and the VDD for the 4-level input is 2.5 V.
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