OMAPL137-HT Datasheet, PDF (389/444 Pages) Texas Instruments – Multimedia Device

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astm_clk
astm_d[3:0]
Public Version
STM1
STM2
STM3
STM4
STM4
STM4
STM4
Figure 5-134. STM—MIPI DDR Transmit Mode
OMAP4460
SWPS046A – JANUARY 2012
SWPS040-091
5.8.1.2.2.2 STM—MIPI Transmit—SDR Mode
Table 5-222 assumes testing over the recommended operating conditions and electrical characteristic
conditions below (see Figure 5-135).
Table 5-221. STM Timing Conditions—MIPI SDR Transmit Mode^(1)(3)(8)
TIMING CONDITION PARAMETER
VALUE
UNIT
PCB Conditions⁽⁶⁾⁽⁷⁾
MIN
MAX
Number of external peripherals
Far end load
Trace length
1
10⁽⁴⁾
pF
10⁽⁵⁾
cm
Characteristics impedance
45
60
Ω
(1) IO settings (Balls in Option 1: M2 / N2 / P2 / V1 / V2⁽²⁾
Balls in Option 2: AA4 / AB2 / AB3 / AB4 / AC4⁽²⁾
Balls in Option 3: M2 / N2⁽²⁾): DS0 = 1.
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / I/O cells with Configurable Output Driver Impedance section of the
OMAP4460 TRM.
(2) For more information regarding the subsystem multiplexing, see Section 2.4.5.4, STM.
(3) In this table the rise and fall times are calculated for 20% to 80% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(4) Either use a far end load less than 10 pF or, add an external buffer in case of higher loads.
(5) Either use a maximum trace length equals to 10 cm or, a 5-cm cable and a 5-cm PCB.
(6) A serial resistor of 15 Ω is recommended to be added to limit the overshoot and the undershoot on far end signals.
(7) It is also recommended to minimize the number of vias by layer transitions.
(8) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
Table 5-222. STM Switching Characteristics—MIPI SDR Transmit Mode⁽⁴⁾
NO.
STM1
STM2
STM3
STM4
PARAMETER
1 / t_c(clk)
t_w(clkH)
t_w(clkL)
t_dc(clk)
t_j(clk)
t_R(clk)
t_F(clk)
t_d(clk-dataV)
t_R(DO)
t_F(DO)
Frequency⁽¹⁾, output clock astm_clk
Pulse duration, output clock astm_clk high
Pulse duration, output clock astm_clk low
Duty cycle error, output clock astm_clk
Jitter standard deviation⁽³⁾, output clock astm_clk
Rise time, output clock astm_clk
Fall time, output clock astm_clk
Delay time, output clock astm_clk low/high to
output control astm_d[3:0] valid
Rise time, output data astm_d[3:0]
Fall time, output data astm_d[3:0]
OPP100, OPP119
MIN
MAX
100
0.5*P⁽²⁾
0.5*P⁽²⁾
–500
500
65
1.73
1.73
–2.296
2.296
1.73
1.73
OPP50
MIN
MAX
100
0.5*P⁽²⁾
0.5*P⁽²⁾
–1000
1000
129
6.90
6.90
–6.313
6.313
6.90
6.90
UNIT
MHz
ns
ns
ps
ps
ns
ns
ns
ns
ns
Copyright © 2012, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 389
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