OMAPL137-HT Datasheet, PDF (272/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
www.ti.com
5.6.1.1.2.2 McBSP1, McBSP2, and McBSP3 Set#1—TDM / Half-Cycle—12MHz, 5-pF Load Capacitance
Table 5-52 through Table 5-55 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-61 and Figure 5-62).
Table 5-51. McBSP1, McBSP2, and McBSP3 Set#1 Timing Conditions—TDM / Half-Cycle^(1)(2)(3)
SYSTEM CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
600
6500
ps
600
6500
ps
Number of external peripherals
1
Far end load
5
pF
Trace length
9
cm
Characteristics impedance
20
60
Ω
(1) IO settings: MB[1:0] = 10 and LB0 = 0 McBSP3 Set#1 means the following balls: AG25, AF25, AE25, AF26.
For more information, see Control Module / Control Module Functional Description/ Functional Register Description / Signal Integrity
Parameter Control Registers with Pad Group Assignment / 50-Ω Output Buffer I/Os with Combined Mode and Load Settings section of
the OMAP4460 TRM.
(2) In this table the rise and fall times are calculated for 10% to 90% of VDDS. For more information on the corresponding OMAP4 VDDS
power supply name, see Table 2-1, POWER [9] column with the ball name.
(3) To have an idea of the output OMAP4 ball load supported for this application, you can consider the following:
Output OMAP4 ball load = Far End load + 1.34 pF/cm typical x trace length (cm).
5.6.1.1.2.2.1 McBSP1, McBSP2, and McBSP3 Set#1—TDM / Half-Cycle—Master Mode
Table 5-52. McBSP1, McBSP2, and McBSP3 Set#1 Timing Requirements—TDM / Half-Cycle—Master
Mode^(1)(3)(6)
NO.
PARAMETER
OPP100, OPP119
OPP50
UNIT
1 / t_c(clks)
t_w(clksL)
t_w(clksH)
t_dc(clks)
Frequency, input abe_clks⁽⁵⁾ clock
Typical pulse duration, input abe_clks low
Typical pulse duration, output abe_clks high
Duty cycle error, input abe_clks
MIN
MAX
12.288⁽⁵⁾
0.5 * P⁽⁴⁾
0.5 * P⁽⁴⁾
–0.05 *
0.05 *
P⁽⁴⁾ + 610 P⁽⁴⁾ – 610
MIN
MAX
6.144⁽⁵⁾
0.5 * P⁽⁴⁾
0.5 * P⁽⁴⁾
–0.05 *
0.05 *
P⁽⁴⁾ + 610 P⁽⁴⁾ – 610
MHz
ns
ns
ps
BM5
t_j(clks)
t_{su(drV-clkAE)}
Jitter peak to peak, input abe_clks
Setup time, abe_mcbspx_dr valid before
abe_mcbspx_clk⁽²⁾ active edge
300
300
ps
11.3
24.3
ns
BM6
t_h(clkAE-drV)
Hold time, abe_mcbspx_dr valid after
–2.4
–2.4
ns
abe_mcbspx_clk⁽²⁾ active edge
(1) The timings apply to all configurations regardless of abe_mcbspx_clk polarity and which clock edges are used to drive output data and
capture input data.
(2) abe_mcbspx_clk corresponds to either abe_mcbspx_clkx or abe_mcbspx_clkr; abe_mcbspx_clkr is available in 6-pin mode only.
(3) In abe_mcbspx, x is equal to 1, or 2, or 3 Set#1 (Balls: AG25, AF25, AE25, AF26).
(4) P = abe_clks input clock period in ns
(5) The McPDM interface can be used at the same time with one or more McBSP (interface 1, 2, or 3). In this case, abe_clks clock is
shared, that means identical, between McPDM and McBSP. As a consequence, the minimum clock frequency between McPDM and
McBSP, input jitter, and duty cycle must be considered between both interfaces.
(6) See DM Operating Condition Addendum for CORE OPP voltages.
Table 5-53. McBSP1, McBSP2, and McBSP3 Set#1 Switching Characteristics—TDM / Half-Cycle—Master
272 Timing Requirements and Switching Characteristics
Submit Documentation Feedback
Product Folder Link(s): OMAP4460
Copyright © 2012, Texas Instruments Incorporated