OMAPL137-HT Datasheet, PDF (290/444 Pages) Texas Instruments – Multimedia Device

OMAP4460
Public Version
SWPS046A – JANUARY 2012
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Table 5-74. McSPI1 Timing Requirements—Slave Mode⁽⁴⁾⁽⁷⁾ (continued)
NO.
PARAMETER
16 MHz SET
8 MHz SET
UNIT
MIN
MAX
MIN
MAX
SS5
t_{h(clkAE-SIMO)}
Hold time, mcspi1_simo valid after
12.82
28.61
ns
mcspi1_clk⁽⁵⁾ active edge
SS8
t_su(CS-CLKAE)
Setup time, mcspi1_cs0 valid before
12.82
28.61
ns
mcspi1_clk⁽⁵⁾ first edge
SS9
t_h(clkAE-CS)
Hold time, mcspi1_cs0 valid after
12.82
28.61
ns
mcspi1_clk⁽⁵⁾ last edge
(1) Related to the input maximum frequency supported by the McSPI module.
(2) P = mcspi1_clk period in ns
(3) Maximum cycle jitter supported by mcspi1_clk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
(5) This timing applies to all configurations regardless of mcspi1_clk polarity and which clock edges are used to drive output data and
capture input data.
(6) With other system conditions (for instance with a less jitter and duty cycle error source clock), 24 MHz of clock frequency could be
reached.
(7) The timings requirements described are applicable to both CORE OPP50 and OPP100 operating points.
Table 5-75. McSPI1 Switching Characteristics—Slave Mode⁽²⁾⁽³⁾
NO.
PARAMETER
16 MHz SET⁽³⁾
8 MHz SET⁽³⁾
UNIT
MIN
MAX
MIN
MAX
SS6
t_d(clk-SOMI) Delay time, mcspi1_clk⁽¹⁾ active edge to
mcspi1_somi transition
–4.66
18.41
–12.01
37.32
ns
SS7
t_d(CS-SOMI) Delay time, mcspi1_cs0 active edge PHA = 0⁽²⁾
to mcspi1_somi transition
18.41
37.32
ns
t_R(SOMI)
t_F(SOMI)
Rise time, mcspi1_somi
Fall time, mcspi1_somi
4000.0
4000.0
4000.0
ps
4000.0
ps
(1) The polarity of mcspi1_clk and the active edge (rising or falling) on which mcspi1_simo is driven and mcspi1_somi is latched is all
software configurable:
– mcspi1_clk phase programmable with the bit PHA of MCSPI_Ch(i)CONF register: PHA = 0 (Modes 0 and 2).
For more information, see the McSPI environment chapter, Data Format Configurations section of the OMAP4460 TRM for modes and
phase correspondence description.
(2) This timing applies to all configurations regardless of mcspi1_clk polarity and which clock edges are used to drive output data and
capture input data.
(3) The timings requirements described are applicable to both CORE OPP50 and OPP100 operating points.
5.6.3.1.2 McSPI2 and McSPI4
Table 5-77 and Table 5-78 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-68 and Figure 5-69).
Table 5-76. McSPI2 and McSPI4 Timing Conditions—Slave Mode^(1)(2)(3)
SYSTEM CONDITION PARAMETER
Input Conditions
t_R
Input signal rise time
t_F
Input signal fall time
PCB Conditions
Number of external peripherals
Far end load
Trace length
Characteristics impedance
VALUE
MIN
MAX
1.00
4.00
1.00
4.00
-
5
2
5
20
60
UNIT
ns
ns
pF
cm
Ω
290 Timing Requirements and Switching Characteristics
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